[PATCH] D83045: [AArch64][SVE] Add FP unpredicated to predicated two-op codegen

[Cameron McInally via Phabricator via llvm-commits]

cameron.mcinally added a comment.

> I initially created an unpredicated intrinsic for this, because I didn't find any other way of generating the unpredicated fmin, fmax, etc. So I would appreciate any suggestions as to how to generate those unpredicated instructions without having to add more intrinsics.

I might be missing the motivation for the unpredicated intrinsic, but in the non-scalable world an unpredicated operation would be canonicalized as a predicated intrinsic with all-1s mask. That would then be lowered during ISel. Something like:

  %mask = shufflevector <vscale x 4 x i1> 1, <vscale x 4 x i1> undef, <vscale x 4 x i32> zeroinitializer
  %res = call <vscale x 4 x float> @llvm.aarch64.sve.fmin.nxv4f32(
    <vscale x 4 x i1> %mask
    <vscale x 4 x float> %a,
    <vscale x 4 x float> %b)

X86 does something similar in `X86ISelLowering.cpp:getVectorMaskingNode(...)`, although it's not really apples-to-apples since X86's masks are represented differently.



================
Comment at: llvm/include/llvm/IR/IntrinsicsAArch64.td:1749
+
+
 def int_aarch64_sve_fmaxnm     : AdvSIMD_Pred2VectorArg_Intrinsic;
----------------
Unnecessary whitespace change?

There are a couple of these in this patch.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1579
   }
-#undef MAKE_CASE
   return nullptr;
 }
----------------
Was this #undef intentionally removed?



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:11909
+    return combineToSVEPred(N, DAG, AArch64ISD::FMINNM);
   }
+
----------------
This looks good, but it may be table-worthy, if this is the way forward. X86 does something similar in `llvm/lib/Target/X86/X86IntrinsicsInfo.h`. Just a heads up.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D83045/new/

https://reviews.llvm.org/D83045