[PATCH] D82788: AMDGPU: Fix alignment requirements for 96bit and 128bit local loads and stores

[Mirko Brkusanin via Phabricator via llvm-commits]

mbrkusanin marked 4 inline comments as done.
mbrkusanin added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:1377
+      // ds_read/write_b96 require 16-byte alignment. gfx9 and onward has
+      // unaligned access support but windows likes to keep it dword aligned.
+      bool IsGFX9Plus = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9;
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nhaehnle wrote:
> arsenm wrote:
> > nhaehnle wrote:
> > > arsenm wrote:
> > > > This is a windows driver bug and doesn't deserve mentioning here. We do not know what the host OS is
> > > I agree that it's a bug, but I find it reasonable to mention it here. I'd change the comment though to specifically call out that this should be considered a bug in the Windows KMD.
> > It's not specific to this instance though, this belongs with the place where we assume unaligned access for amdhsa
> Okay, that's fair.
Is the new wording ok?


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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:1378-1379
+      // unaligned access support but windows likes to keep it dword aligned.
+      bool IsGFX9Plus = Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9;
+      bool Aligned = Align % (IsGFX9Plus ? 4 : 16) == 0;
+      if (IsFast)
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arsenm wrote:
> This should use an explicit subtarget feature check, not for the generation. The subtarget feature also theoretically captures this being a setting. We have hasUnalignedBufferAccess already (I believe the same control is used for DS and regular memory instructions, but I'm not sure)
Added hasUnalignedDSAccess.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82788/new/

https://reviews.llvm.org/D82788