[PATCH] D83020: [AMDGPU] Avoid using s_cmpk when src0 is not register

[Ruiling, Song via Phabricator via llvm-commits]

ruiling updated this revision to Diff 275003.
ruiling added a comment.

auto-generate the checks in test


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D83020/new/

https://reviews.llvm.org/D83020

Files:
  llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
  llvm/test/CodeGen/AMDGPU/cmp_shrink.mir


Index: llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/cmp_shrink.mir
@@ -0,0 +1,11 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass si-shrink-instructions -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name:             not_shrink_icmp
+body:             |
+  bb.0:
+    ; GCN-LABEL: name: not_shrink_icmp
+    ; GCN: S_CMP_GT_I32 1, 65, implicit-def $scc
+    S_CMP_GT_I32 1, 65, implicit-def $scc
+...
Index: llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
+++ llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp
@@ -185,6 +185,11 @@
   if (!MI.getOperand(0).isReg())
     TII->commuteInstruction(MI, false, 0, 1);
 
+  // cmpk requires src0 to be a register
+  const MachineOperand &Src0 = MI.getOperand(0);
+  if (!Src0.isReg())
+    return;
+
   const MachineOperand &Src1 = MI.getOperand(1);
   if (!Src1.isImm())
     return;


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