[PATCH] D82871: [SVE] Custom ISel for fixed length extract/insert_subvector.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm marked 2 inline comments as done.
paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:3366
+    if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue() != 0)
+      break;
+
----------------
efriedma wrote:
> Do we need the isPackedVectorType check here as well?
The code in LowerEXTRACT_SUBVECTOR should preclude that case, but I can add some asserts.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82871/new/

https://reviews.llvm.org/D82871