[PATCH] D82871: [SVE] Custom ISel for fixed length extract/insert_subvector.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:3366
+    if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue() != 0)
+      break;
+
----------------
Do we need the isPackedVectorType check here as well?


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp:3385
+
+  case ISD::INSERT_SUBVECTOR: {
+    // Bail when not a "cast" like insert_subvector.
----------------
paulwalker-arm wrote:
> efriedma wrote:
> > There isn't any corresponding code for INSERT_SUBVECTOR in AArch64ISelLowering?
> Unlike EXTRACT_SUBVECTOR, AArch64ISelLowering didn't have any custom lowering for INSERT_SUBVECTOR for any vector types.  For this reason I assumed the defaults were fine.  My new usage when lowering fixed length to SVE only uses the legal variants so doesn't introduce any new requirements.
In theory, you need exactly the same code.

Realistically, I'm not sure target-independent code will actually ever create an insert_subvector with a non-zero index.  I briefly tried grepping through the relevant code, and couldn't find anything. I guess we could ignore the issue for now.


Repository:
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  https://reviews.llvm.org/D82871/new/

https://reviews.llvm.org/D82871