[PATCH] D81076: [PowerPC] Custom lower rotl v1i128 to vector_shuffle.

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang added a comment.

In D81076#2110955 <https://reviews.llvm.org/D81076#2110955>, @shawnl wrote:

> It can be done with xor to produce a zero vector, however I can't get the code-gen to generate something that doesn't use the TOC.


We can use the xor for zero vector, but for the mask, we have to load it from constant pool. So, I don't see the benefit with the transformation for this case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D81076/new/

https://reviews.llvm.org/D81076