[PATCH] D81076: [PowerPC] Custom lower rotl v1i128 to vector_shuffle.

Shawn Landden via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Jun 24 02:40:14 PDT 2020

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shawnl added a comment.

It can be done with xor to produce a zero vector, however I can't get the code-gen to generate something that doesn't use the TOC.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D81076/new/

https://reviews.llvm.org/D81076

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