[llvm] 66da87d - [RISCV] Assemble/Disassemble v-ext instructions.
Hsiangkai Wang via llvm-commits
llvm-commits at lists.llvm.org
Sat Jun 27 09:54:38 PDT 2020
Author: Hsiangkai Wang
Date: 2020-06-28T00:54:07+08:00
New Revision: 66da87dcbaf91fa3393ce80c687e9c2d133ee3ca
URL: https://github.com/llvm/llvm-project/commit/66da87dcbaf91fa3393ce80c687e9c2d133ee3ca
DIFF: https://github.com/llvm/llvm-project/commit/66da87dcbaf91fa3393ce80c687e9c2d133ee3ca.diff
LOG: [RISCV] Assemble/Disassemble v-ext instructions.
Assemble/disassemble RISC-V V extension instructions according to
latest version spec in https://github.com/riscv/riscv-v-spec/.
I have tested this patch using GNU toolchain. The encoding is aligned
to GNU assembler output. In this patch, there is a test case for each
instruction at least.
The V register definition is just for assemble/disassemble. Its type
is not important in this stage. I think it will be reviewed and modified
as we want to do codegen for scalable vector types.
This patch does not include Zvamo, Zvlsseg, and Zvediv.
Differential revision: https://reviews.llvm.org/D69987
Added:
llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
llvm/lib/Target/RISCV/RISCVInstrInfoV.td
llvm/test/MC/RISCV/rvv/add.s
llvm/test/MC/RISCV/rvv/and.s
llvm/test/MC/RISCV/rvv/clip.s
llvm/test/MC/RISCV/rvv/compare.s
llvm/test/MC/RISCV/rvv/convert.s
llvm/test/MC/RISCV/rvv/div.s
llvm/test/MC/RISCV/rvv/fadd.s
llvm/test/MC/RISCV/rvv/fcompare.s
llvm/test/MC/RISCV/rvv/fdiv.s
llvm/test/MC/RISCV/rvv/fmacc.s
llvm/test/MC/RISCV/rvv/fminmax.s
llvm/test/MC/RISCV/rvv/fmul.s
llvm/test/MC/RISCV/rvv/fmv.s
llvm/test/MC/RISCV/rvv/fothers.s
llvm/test/MC/RISCV/rvv/freduction.s
llvm/test/MC/RISCV/rvv/fsub.s
llvm/test/MC/RISCV/rvv/invalid.s
llvm/test/MC/RISCV/rvv/load.s
llvm/test/MC/RISCV/rvv/macc.s
llvm/test/MC/RISCV/rvv/mask.s
llvm/test/MC/RISCV/rvv/minmax.s
llvm/test/MC/RISCV/rvv/mul.s
llvm/test/MC/RISCV/rvv/mv.s
llvm/test/MC/RISCV/rvv/or.s
llvm/test/MC/RISCV/rvv/others.s
llvm/test/MC/RISCV/rvv/reduction.s
llvm/test/MC/RISCV/rvv/shift.s
llvm/test/MC/RISCV/rvv/sign-injection.s
llvm/test/MC/RISCV/rvv/snippet.s
llvm/test/MC/RISCV/rvv/store.s
llvm/test/MC/RISCV/rvv/sub.s
llvm/test/MC/RISCV/rvv/vsetvl.s
llvm/test/MC/RISCV/rvv/xor.s
Modified:
llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
llvm/lib/Target/RISCV/RISCVRegisterInfo.td
llvm/lib/Target/RISCV/RISCVSchedRocket32.td
llvm/lib/Target/RISCV/RISCVSchedRocket64.td
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/lib/Target/RISCV/RISCVSystemOperands.td
llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
index e239870662bb..854a6b82be76 100644
--- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
+++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
@@ -10,10 +10,13 @@
#include "MCTargetDesc/RISCVMCExpr.h"
#include "MCTargetDesc/RISCVMCTargetDesc.h"
#include "MCTargetDesc/RISCVTargetStreamer.h"
+#include "RISCVInstrInfo.h"
#include "TargetInfo/RISCVTargetInfo.h"
#include "Utils/RISCVBaseInfo.h"
#include "Utils/RISCVMatInt.h"
#include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SmallBitVector.h"
+#include "llvm/ADT/SmallString.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringSwitch.h"
@@ -128,6 +131,9 @@ class RISCVAsmParser : public MCTargetAsmParser {
// 'add' is an overloaded mnemonic.
bool checkPseudoAddTPRel(MCInst &Inst, OperandVector &Operands);
+ // Check instruction constraints.
+ bool validateInstruction(MCInst &Inst, OperandVector &Operands);
+
/// Helper for processing MC instructions that have been successfully matched
/// by MatchAndEmitInstruction. Modifications to the emitted instructions,
/// like the expansion of pseudo instructions (e.g., "li"), can be performed
@@ -150,6 +156,8 @@ class RISCVAsmParser : public MCTargetAsmParser {
OperandMatchResultTy parseCallSymbol(OperandVector &Operands);
OperandMatchResultTy parsePseudoJumpSymbol(OperandVector &Operands);
OperandMatchResultTy parseJALOffset(OperandVector &Operands);
+ OperandMatchResultTy parseVTypeI(OperandVector &Operands);
+ OperandMatchResultTy parseMaskReg(OperandVector &Operands);
bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
@@ -198,6 +206,8 @@ class RISCVAsmParser : public MCTargetAsmParser {
return false;
}
+ std::unique_ptr<RISCVOperand> defaultMaskRegOp() const;
+
public:
enum RISCVMatchResultTy {
Match_Dummy = FIRST_TARGET_MATCH_RESULT_TY,
@@ -245,7 +255,8 @@ struct RISCVOperand : public MCParsedAsmOperand {
Token,
Register,
Immediate,
- SystemRegister
+ SystemRegister,
+ VType,
} Kind;
bool IsRV64;
@@ -266,12 +277,32 @@ struct RISCVOperand : public MCParsedAsmOperand {
// e.g.: read/write or user/supervisor/machine privileges.
};
+ enum class VSEW {
+ SEW_8 = 0,
+ SEW_16,
+ SEW_32,
+ SEW_64,
+ SEW_128,
+ SEW_256,
+ SEW_512,
+ SEW_1024,
+ };
+
+ enum class VLMUL { LMUL_1 = 0, LMUL_2, LMUL_4, LMUL_8 };
+
+ struct VTypeOp {
+ VSEW Sew;
+ VLMUL Lmul;
+ unsigned Encoding;
+ };
+
SMLoc StartLoc, EndLoc;
union {
StringRef Tok;
RegOp Reg;
ImmOp Imm;
struct SysRegOp SysReg;
+ struct VTypeOp VType;
};
RISCVOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
@@ -295,14 +326,21 @@ struct RISCVOperand : public MCParsedAsmOperand {
case KindTy::SystemRegister:
SysReg = o.SysReg;
break;
+ case KindTy::VType:
+ VType = o.VType;
+ break;
}
}
bool isToken() const override { return Kind == KindTy::Token; }
bool isReg() const override { return Kind == KindTy::Register; }
+ bool isV0Reg() const {
+ return Kind == KindTy::Register && Reg.RegNum == RISCV::V0;
+ }
bool isImm() const override { return Kind == KindTy::Immediate; }
bool isMem() const override { return false; }
bool isSystemRegister() const { return Kind == KindTy::SystemRegister; }
+ bool isVType() const { return Kind == KindTy::VType; }
bool isGPR() const {
return Kind == KindTy::Register &&
@@ -386,6 +424,8 @@ struct RISCVOperand : public MCParsedAsmOperand {
bool isCSRSystemRegister() const { return isSystemRegister(); }
+ bool isVTypeI() const { return isVType(); }
+
/// Return true if the operand is a valid for the fence instruction e.g.
/// ('iorw').
bool isFenceArg() const {
@@ -493,6 +533,15 @@ struct RISCVOperand : public MCParsedAsmOperand {
VK == RISCVMCExpr::VK_RISCV_None;
}
+ bool isSImm5() const {
+ if (!isImm())
+ return false;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ int64_t Imm;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ return IsConstantImm && isInt<5>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
+ }
+
bool isSImm6() const {
if (!isImm())
return false;
@@ -658,6 +707,16 @@ struct RISCVOperand : public MCParsedAsmOperand {
return IsConstantImm && (Imm == 0) && VK == RISCVMCExpr::VK_RISCV_None;
}
+ bool isSImm5Plus1() const {
+ if (!isImm())
+ return false;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ int64_t Imm;
+ bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK);
+ return IsConstantImm && isInt<5>(Imm - 1) &&
+ VK == RISCVMCExpr::VK_RISCV_None;
+ }
+
/// getStartLoc - Gets location of the first token of this operand
SMLoc getStartLoc() const override { return StartLoc; }
/// getEndLoc - Gets location of the last token of this operand
@@ -685,6 +744,51 @@ struct RISCVOperand : public MCParsedAsmOperand {
return Tok;
}
+ static StringRef getSEWStr(VSEW Sew) {
+ switch (Sew) {
+ case VSEW::SEW_8:
+ return "e8";
+ case VSEW::SEW_16:
+ return "e16";
+ case VSEW::SEW_32:
+ return "e32";
+ case VSEW::SEW_64:
+ return "e64";
+ case VSEW::SEW_128:
+ return "e128";
+ case VSEW::SEW_256:
+ return "e256";
+ case VSEW::SEW_512:
+ return "e512";
+ case VSEW::SEW_1024:
+ return "e1024";
+ }
+ return "";
+ }
+
+ static StringRef getLMULStr(VLMUL Lmul) {
+ switch (Lmul) {
+ case VLMUL::LMUL_1:
+ return "m1";
+ case VLMUL::LMUL_2:
+ return "m2";
+ case VLMUL::LMUL_4:
+ return "m4";
+ case VLMUL::LMUL_8:
+ return "m8";
+ }
+ return "";
+ }
+
+ StringRef getVType(SmallString<32> &Buf) const {
+ assert(Kind == KindTy::VType && "Invalid access!");
+ Buf.append(getSEWStr(VType.Sew));
+ Buf.append(",");
+ Buf.append(getLMULStr(VType.Lmul));
+
+ return Buf.str();
+ }
+
void print(raw_ostream &OS) const override {
switch (Kind) {
case KindTy::Immediate:
@@ -700,6 +804,10 @@ struct RISCVOperand : public MCParsedAsmOperand {
case KindTy::SystemRegister:
OS << "<sysreg: " << getSysReg() << '>';
break;
+ case KindTy::VType:
+ SmallString<32> VTypeBuf;
+ OS << "<vtype: " << getVType(VTypeBuf) << '>';
+ break;
}
}
@@ -744,6 +852,20 @@ struct RISCVOperand : public MCParsedAsmOperand {
return Op;
}
+ static std::unique_ptr<RISCVOperand> createVType(APInt Sew, APInt Lmul,
+ SMLoc S, bool IsRV64) {
+ auto Op = std::make_unique<RISCVOperand>(KindTy::VType);
+ Sew.ashrInPlace(3);
+ unsigned SewLog2 = Sew.logBase2();
+ unsigned LmulLog2 = Lmul.logBase2();
+ Op->VType.Sew = static_cast<VSEW>(SewLog2);
+ Op->VType.Lmul = static_cast<VLMUL>(LmulLog2);
+ Op->VType.Encoding = (SewLog2 << 2) | LmulLog2;
+ Op->StartLoc = S;
+ Op->IsRV64 = IsRV64;
+ return Op;
+ }
+
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
assert(Expr && "Expr shouldn't be null!");
int64_t Imm = 0;
@@ -767,6 +889,15 @@ struct RISCVOperand : public MCParsedAsmOperand {
addExpr(Inst, getImm());
}
+ void addSImm5Plus1Operands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ int64_t Imm = 0;
+ RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None;
+ bool IsConstant = evaluateConstantImm(getImm(), Imm, VK);
+ assert(IsConstant && "Expect constant value!");
+ Inst.addOperand(MCOperand::createImm(Imm - 1));
+ }
+
void addFenceArgOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
// isFenceArg has validated the operand, meaning this cast is safe
@@ -791,6 +922,11 @@ struct RISCVOperand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createImm(SysReg.Encoding));
}
+ void addVTypeIOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::createImm(VType.Encoding));
+ }
+
// Returns the rounding mode represented by this RISCVOperand. Should only
// be called after checking isFRMArg.
RISCVFPRndMode::RoundingMode getRoundingMode() const {
@@ -868,6 +1004,8 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
default:
break;
case Match_Success:
+ if (validateInstruction(Inst, Operands))
+ return true;
return processInstruction(Inst, IDLoc, Operands, Out);
case Match_MissingFeature: {
assert(MissingFeatures.any() && "Unknown missing features!");
@@ -1040,6 +1178,20 @@ bool RISCVAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
return Error(ErrorLoc, "operand must be a symbol with %tprel_add modifier");
}
+ case Match_InvalidVTypeI: {
+ SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
+ return Error(ErrorLoc,
+ "operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]");
+ }
+ case Match_InvalidVMaskRegister: {
+ SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
+ return Error(ErrorLoc, "operand must be v0.t");
+ }
+ case Match_InvalidSImm5Plus1: {
+ return generateImmOutOfRangeError(Operands, ErrorInfo, -(1 << 4) + 1,
+ (1 << 4),
+ "immediate must be in the range");
+ }
}
llvm_unreachable("Unknown match type detected!");
@@ -1391,6 +1543,74 @@ OperandMatchResultTy RISCVAsmParser::parseJALOffset(OperandVector &Operands) {
return parseImmediate(Operands);
}
+OperandMatchResultTy RISCVAsmParser::parseVTypeI(OperandVector &Operands) {
+ SMLoc S = getLoc();
+ if (getLexer().getKind() != AsmToken::Identifier)
+ return MatchOperand_NoMatch;
+
+ // Parse "e8,m1"
+ StringRef Name = getLexer().getTok().getIdentifier();
+ if (!Name.consume_front("e"))
+ return MatchOperand_NoMatch;
+ APInt Sew(16, Name, 10);
+ if (Sew != 8 && Sew != 16 && Sew != 32 && Sew != 64 && Sew != 128 &&
+ Sew != 256 && Sew != 512 && Sew != 1024)
+ return MatchOperand_NoMatch;
+ getLexer().Lex();
+
+ if (getLexer().getKind() == AsmToken::EndOfStatement) {
+ Operands.push_back(
+ RISCVOperand::createVType(Sew, APInt(16, 1), S, isRV64()));
+
+ return MatchOperand_Success;
+ }
+
+ if (!getLexer().is(AsmToken::Comma))
+ return MatchOperand_NoMatch;
+ getLexer().Lex();
+
+ Name = getLexer().getTok().getIdentifier();
+ if (!Name.consume_front("m"))
+ return MatchOperand_NoMatch;
+ APInt Lmul(16, Name, 10);
+ if (Lmul != 1 && Lmul != 2 && Lmul != 4 && Lmul != 8)
+ return MatchOperand_NoMatch;
+ getLexer().Lex();
+
+ if (getLexer().getKind() != AsmToken::EndOfStatement)
+ return MatchOperand_NoMatch;
+
+ Operands.push_back(RISCVOperand::createVType(Sew, Lmul, S, isRV64()));
+
+ return MatchOperand_Success;
+}
+
+OperandMatchResultTy RISCVAsmParser::parseMaskReg(OperandVector &Operands) {
+ switch (getLexer().getKind()) {
+ default:
+ return MatchOperand_NoMatch;
+ case AsmToken::Identifier:
+ StringRef Name = getLexer().getTok().getIdentifier();
+ if (!Name.consume_back(".t")) {
+ Error(getLoc(), "expected '.t' suffix");
+ return MatchOperand_ParseFail;
+ }
+ Register RegNo;
+ matchRegisterNameHelper(isRV32E(), RegNo, Name);
+
+ if (RegNo == RISCV::NoRegister)
+ return MatchOperand_NoMatch;
+ if (RegNo != RISCV::V0)
+ return MatchOperand_NoMatch;
+ SMLoc S = getLoc();
+ SMLoc E = SMLoc::getFromPointer(S.getPointer() - 1);
+ getLexer().Lex();
+ Operands.push_back(RISCVOperand::createReg(RegNo, S, E, isRV64()));
+ }
+
+ return MatchOperand_Success;
+}
+
OperandMatchResultTy
RISCVAsmParser::parseMemOpBaseReg(OperandVector &Operands) {
if (getLexer().isNot(AsmToken::LParen)) {
@@ -2046,6 +2266,89 @@ bool RISCVAsmParser::checkPseudoAddTPRel(MCInst &Inst,
return false;
}
+std::unique_ptr<RISCVOperand> RISCVAsmParser::defaultMaskRegOp() const {
+ return RISCVOperand::createReg(RISCV::NoRegister, llvm::SMLoc(),
+ llvm::SMLoc(), isRV64());
+}
+
+bool RISCVAsmParser::validateInstruction(MCInst &Inst,
+ OperandVector &Operands) {
+ const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
+ unsigned TargetFlags =
+ (MCID.TSFlags >> RISCV::ConstraintOffset) & RISCV::ConstraintMask;
+ if (TargetFlags == RISCV::NoConstraint)
+ return false;
+
+ unsigned DestReg = Inst.getOperand(0).getReg();
+ // Operands[1] will be the first operand, DestReg.
+ SMLoc Loc = Operands[1]->getStartLoc();
+ if ((TargetFlags == RISCV::WidenV) || (TargetFlags == RISCV::WidenW) ||
+ (TargetFlags == RISCV::SlideUp) || (TargetFlags == RISCV::Vrgather) ||
+ (TargetFlags == RISCV::Vcompress)) {
+ if (TargetFlags != RISCV::WidenW) {
+ unsigned Src2Reg = Inst.getOperand(1).getReg();
+ if (DestReg == Src2Reg)
+ return Error(Loc, "The destination vector register group cannot overlap"
+ " the source vector register group.");
+ if (TargetFlags == RISCV::WidenV) {
+ // Assume DestReg LMUL is 2 at least for widening/narrowing operations.
+ if (DestReg + 1 == Src2Reg)
+ return Error(Loc,
+ "The destination vector register group cannot overlap"
+ " the source vector register group.");
+ }
+ }
+ if (Inst.getOperand(2).isReg()) {
+ unsigned Src1Reg = Inst.getOperand(2).getReg();
+ if (DestReg == Src1Reg)
+ return Error(Loc, "The destination vector register group cannot overlap"
+ " the source vector register group.");
+ if (TargetFlags == RISCV::WidenV || TargetFlags == RISCV::WidenW) {
+ // Assume DestReg LMUL is 2 at least for widening/narrowing operations.
+ if (DestReg + 1 == Src1Reg)
+ return Error(Loc,
+ "The destination vector register group cannot overlap"
+ " the source vector register group.");
+ }
+ }
+ if (Inst.getNumOperands() == 4) {
+ unsigned MaskReg = Inst.getOperand(3).getReg();
+
+ if (DestReg == MaskReg)
+ return Error(Loc, "The destination vector register group cannot overlap"
+ " the mask register.");
+ }
+ } else if (TargetFlags == RISCV::Narrow) {
+ unsigned Src2Reg = Inst.getOperand(1).getReg();
+ if (DestReg == Src2Reg)
+ return Error(Loc, "The destination vector register group cannot overlap"
+ " the source vector register group.");
+ // Assume Src2Reg LMUL is 2 at least for widening/narrowing operations.
+ if (DestReg == Src2Reg + 1)
+ return Error(Loc, "The destination vector register group cannot overlap"
+ " the source vector register group.");
+ } else if (TargetFlags == RISCV::WidenCvt || TargetFlags == RISCV::Iota) {
+ unsigned Src2Reg = Inst.getOperand(1).getReg();
+ if (DestReg == Src2Reg)
+ return Error(Loc, "The destination vector register group cannot overlap"
+ " the source vector register group.");
+ if (TargetFlags == RISCV::WidenCvt) {
+ // Assume DestReg LMUL is 2 at least for widening/narrowing operations.
+ if (DestReg + 1 == Src2Reg)
+ return Error(Loc, "The destination vector register group cannot overlap"
+ " the source vector register group.");
+ }
+ if (Inst.getNumOperands() == 3) {
+ unsigned MaskReg = Inst.getOperand(2).getReg();
+
+ if (DestReg == MaskReg)
+ return Error(Loc, "The destination vector register group cannot overlap"
+ " the mask register.");
+ }
+ }
+ return false;
+}
+
bool RISCVAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc,
OperandVector &Operands,
MCStreamer &Out) {
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index 92519be87015..37edc19398a5 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -18,6 +18,7 @@
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
#include "llvm/MC/MCFixedLenDisassembler.h"
#include "llvm/MC/MCInst.h"
+#include "llvm/MC/MCInstrInfo.h"
#include "llvm/MC/MCRegisterInfo.h"
#include "llvm/MC/MCSubtargetInfo.h"
#include "llvm/Support/Endian.h"
@@ -31,10 +32,12 @@ typedef MCDisassembler::DecodeStatus DecodeStatus;
namespace {
class RISCVDisassembler : public MCDisassembler {
+ std::unique_ptr<MCInstrInfo const> const MCII;
public:
- RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
- : MCDisassembler(STI, Ctx) {}
+ RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
+ MCInstrInfo const *MCII)
+ : MCDisassembler(STI, Ctx), MCII(MCII) {}
DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address,
@@ -45,7 +48,7 @@ class RISCVDisassembler : public MCDisassembler {
static MCDisassembler *createRISCVDisassembler(const Target &T,
const MCSubtargetInfo &STI,
MCContext &Ctx) {
- return new RISCVDisassembler(STI, Ctx);
+ return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
}
extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVDisassembler() {
@@ -148,6 +151,33 @@ static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
return MCDisassembler::Success;
}
+static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ if (RegNo >= 32)
+ return MCDisassembler::Fail;
+
+ Register Reg = RISCV::V0 + RegNo;
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
+static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address, const void *Decoder) {
+ Register Reg = RISCV::NoRegister;
+ switch (RegNo) {
+ default:
+ return MCDisassembler::Fail;
+ case 0:
+ Reg = RISCV::V0;
+ break;
+ case 1:
+ break;
+ }
+ Inst.addOperand(MCOperand::createReg(Reg));
+ return MCDisassembler::Success;
+}
+
// Add implied SP operand for instructions *SP compressed instructions. The SP
// operand isn't explicitly encoded in the instruction.
static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
index 6cf97dd51baa..eae3e13dbe40 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp
@@ -150,6 +150,39 @@ void RISCVInstPrinter::printAtomicMemOp(const MCInst *MI, unsigned OpNo,
return;
}
+void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &O) {
+ unsigned Imm = MI->getOperand(OpNo).getImm();
+ unsigned Sew = (Imm >> 2) & 0x7;
+ unsigned Lmul = Imm & 0x3;
+
+ Lmul = 0x1 << Lmul;
+ Sew = 0x1 << (Sew + 3);
+ O << "e" << Sew << ",m" << Lmul;
+}
+
+void RISCVInstPrinter::printVMaskReg(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ const MCOperand &MO = MI->getOperand(OpNo);
+
+ assert(MO.isReg() && "printVMaskReg can only print register operands");
+ if (MO.getReg() == RISCV::NoRegister)
+ return;
+ O << ", ";
+ printRegName(O, MO.getReg());
+ O << ".t";
+}
+
+void RISCVInstPrinter::printSImm5Plus1(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI,
+ raw_ostream &O) {
+ const MCOperand &MO = MI->getOperand(OpNo);
+
+ assert(MO.isImm() && "printSImm5Plus1 can only print constant operands");
+ O << MO.getImm() + 1;
+}
+
const char *RISCVInstPrinter::getRegisterName(unsigned RegNo) {
return getRegisterName(RegNo, ArchRegNames ? RISCV::NoRegAltName
: RISCV::ABIRegAltName);
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
index 893524af5466..fdaa00c5f8eb 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.h
@@ -40,6 +40,12 @@ class RISCVInstPrinter : public MCInstPrinter {
raw_ostream &O);
void printAtomicMemOp(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI, raw_ostream &O);
+ void printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
+ raw_ostream &O);
+ void printVMaskReg(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &O);
+ void printSImm5Plus1(const MCInst *MI, unsigned OpNo,
+ const MCSubtargetInfo &STI, raw_ostream &O);
// Autogenerated by tblgen.
void printInstruction(const MCInst *MI, uint64_t Address,
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
index 5139ec5873d8..ae13c00565c4 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
@@ -80,6 +80,10 @@ class RISCVMCCodeEmitter : public MCCodeEmitter {
unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
SmallVectorImpl<MCFixup> &Fixups,
const MCSubtargetInfo &STI) const;
+
+ unsigned getVMaskReg(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const;
};
} // end anonymous namespace
@@ -374,4 +378,20 @@ unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
return 0;
}
+unsigned RISCVMCCodeEmitter::getVMaskReg(const MCInst &MI, unsigned OpNo,
+ SmallVectorImpl<MCFixup> &Fixups,
+ const MCSubtargetInfo &STI) const {
+ MCOperand MO = MI.getOperand(OpNo);
+ assert(MO.isReg() && "Expected a register.");
+
+ switch (MO.getReg()) {
+ default:
+ llvm_unreachable("Invalid mask register.");
+ case RISCV::V0:
+ return 0;
+ case RISCV::NoRegister:
+ return 1;
+ }
+}
+
#include "RISCVGenMCCodeEmitter.inc"
diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td
index 6564e0aa49f1..ec00b256eeab 100644
--- a/llvm/lib/Target/RISCV/RISCV.td
+++ b/llvm/lib/Target/RISCV/RISCV.td
@@ -147,6 +147,14 @@ def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
AssemblerPredicate<(all_of FeatureRVCHints),
"RVC Hint Instructions">;
+def FeatureStdExtV
+ : SubtargetFeature<"experimental-v", "HasStdExtV", "true",
+ "'V' (Vector Instructions)",
+ [FeatureStdExtF]>;
+def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
+ AssemblerPredicate<(all_of FeatureStdExtV),
+ "'V' (Vector Instructions)">;
+
def Feature64Bit
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
def IsRV64 : Predicate<"Subtarget->is64Bit()">,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 3ed10cca5377..a47945a6a515 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -49,6 +49,19 @@ def InstFormatCB : InstFormat<15>;
def InstFormatCJ : InstFormat<16>;
def InstFormatOther : InstFormat<17>;
+class RISCVVConstraint<bits<4> val> {
+ bits<4> Value = val;
+}
+def NoConstraint : RISCVVConstraint<0>;
+def WidenV : RISCVVConstraint<1>;
+def WidenW : RISCVVConstraint<2>;
+def WidenCvt : RISCVVConstraint<3>;
+def Narrow : RISCVVConstraint<4>;
+def Iota : RISCVVConstraint<5>;
+def SlideUp : RISCVVConstraint<6>;
+def Vrgather : RISCVVConstraint<7>;
+def Vcompress : RISCVVConstraint<8>;
+
// The following opcode names match those given in Table 19.1 in the
// RISC-V User-level ISA specification ("RISC-V base opcode map").
class RISCVOpcode<bits<7> val> {
@@ -71,6 +84,7 @@ def OPC_MSUB : RISCVOpcode<0b1000111>;
def OPC_NMSUB : RISCVOpcode<0b1001011>;
def OPC_NMADD : RISCVOpcode<0b1001111>;
def OPC_OP_FP : RISCVOpcode<0b1010011>;
+def OPC_OP_V : RISCVOpcode<0b1010111>;
def OPC_BRANCH : RISCVOpcode<0b1100011>;
def OPC_JALR : RISCVOpcode<0b1100111>;
def OPC_JAL : RISCVOpcode<0b1101111>;
@@ -99,6 +113,10 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
let Pattern = pattern;
let TSFlags{4-0} = format.Value;
+
+ // Defaults
+ RISCVVConstraint RVVConstraint = NoConstraint;
+ let TSFlags{8-5} = RVVConstraint.Value;
}
// Pseudo instructions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
new file mode 100644
index 000000000000..e5f154966ba6
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
@@ -0,0 +1,300 @@
+//===-- RISCVInstrFormatsV.td - RISCV V Instruction Formats --*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the RISC-V V extension instruction formats.
+//
+//===----------------------------------------------------------------------===//
+
+class RISCVVFormat<bits<3> val> {
+ bits<3> Value = val;
+}
+def OPIVV : RISCVVFormat<0b000>;
+def OPFVV : RISCVVFormat<0b001>;
+def OPMVV : RISCVVFormat<0b010>;
+def OPIVI : RISCVVFormat<0b011>;
+def OPIVX : RISCVVFormat<0b100>;
+def OPFVF : RISCVVFormat<0b101>;
+def OPMVX : RISCVVFormat<0b110>;
+
+class RISCVMOP<bits<3> val> {
+ bits<3> Value = val;
+}
+def MOPLDUnitStrideU : RISCVMOP<0b000>;
+def MOPLDStridedU : RISCVMOP<0b010>;
+def MOPLDIndexedU : RISCVMOP<0b011>;
+def MOPLDUnitStrideS : RISCVMOP<0b100>;
+def MOPLDStridedS : RISCVMOP<0b110>;
+def MOPLDIndexedS : RISCVMOP<0b111>;
+
+def MOPSTUnitStride : RISCVMOP<0b000>;
+def MOPSTStrided : RISCVMOP<0b010>;
+def MOPSTIndexedOrder: RISCVMOP<0b011>;
+def MOPSTIndexedUnOrd: RISCVMOP<0b111>;
+
+class RISCVLSUMOP<bits<5> val> {
+ bits<5> Value = val;
+}
+def LUMOPUnitStride : RISCVLSUMOP<0b00000>;
+def LUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
+def LUMOPUnitStrideFF: RISCVLSUMOP<0b10000>;
+def SUMOPUnitStride : RISCVLSUMOP<0b00000>;
+def SUMOPUnitStrideWholeReg : RISCVLSUMOP<0b01000>;
+
+class RISCVWidth<bits<3> val> {
+ bits<3> Value = val;
+}
+def LSWidthVByte : RISCVWidth<0b000>;
+def LSWidthVHalf : RISCVWidth<0b101>;
+def LSWidthVWord : RISCVWidth<0b110>;
+def LSWidthVSEW : RISCVWidth<0b111>;
+
+class RVInstSetVLi<dag outs, dag ins, string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatI> {
+ bits<5> rs1;
+ bits<5> rd;
+ bits<11> vtypei;
+
+ let Inst{31} = 0;
+ let Inst{30-20} = vtypei;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b111;
+ let Inst{11-7} = rd;
+ let Opcode = OPC_OP_V.Value;
+
+ let Defs = [VTYPE, VL];
+}
+
+class RVInstSetVL<dag outs, dag ins, string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> rs2;
+ bits<5> rs1;
+ bits<5> rd;
+
+ let Inst{31} = 1;
+ let Inst{30-25} = 0b000000;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = 0b111;
+ let Inst{11-7} = rd;
+ let Opcode = OPC_OP_V.Value;
+
+ let Defs = [VTYPE, VL];
+}
+
+class RVInstVV<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> vs2;
+ bits<5> vs1;
+ bits<5> vd;
+ bit vm;
+
+ let Inst{31-26} = funct6;
+ let Inst{25} = vm;
+ let Inst{24-20} = vs2;
+ let Inst{19-15} = vs1;
+ let Inst{14-12} = opv.Value;
+ let Inst{11-7} = vd;
+ let Opcode = OPC_OP_V.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+class RVInstVX<bits<6> funct6, RISCVVFormat opv, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> vs2;
+ bits<5> rs1;
+ bits<5> vd;
+ bit vm;
+
+ let Inst{31-26} = funct6;
+ let Inst{25} = vm;
+ let Inst{24-20} = vs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = opv.Value;
+ let Inst{11-7} = vd;
+ let Opcode = OPC_OP_V.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+class RVInstV2<bits<6> funct6, bits<5> vs2, RISCVVFormat opv, dag outs, dag ins,
+ string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> rs1;
+ bits<5> vd;
+ bit vm;
+
+ let Inst{31-26} = funct6;
+ let Inst{25} = vm;
+ let Inst{24-20} = vs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = opv.Value;
+ let Inst{11-7} = vd;
+ let Opcode = OPC_OP_V.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+class RVInstIVI<bits<6> funct6, dag outs, dag ins, string opcodestr,
+ string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> vs2;
+ bits<5> imm;
+ bits<5> vd;
+ bit vm;
+
+ let Inst{31-26} = funct6;
+ let Inst{25} = vm;
+ let Inst{24-20} = vs2;
+ let Inst{19-15} = imm;
+ let Inst{14-12} = 0b011;
+ let Inst{11-7} = vd;
+ let Opcode = OPC_OP_V.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+class RVInstV<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, dag outs,
+ dag ins, string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> vs2;
+ bits<5> vd;
+ bit vm;
+
+ let Inst{31-26} = funct6;
+ let Inst{25} = vm;
+ let Inst{24-20} = vs2;
+ let Inst{19-15} = vs1;
+ let Inst{14-12} = opv.Value;
+ let Inst{11-7} = vd;
+ let Opcode = OPC_OP_V.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+class RVInstVLU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP lumop,
+ RISCVWidth width, dag outs, dag ins, string opcodestr,
+ string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> rs1;
+ bits<5> vd;
+ bit vm;
+
+ let Inst{31-29} = nf;
+ let Inst{28-26} = mop.Value;
+ let Inst{25} = vm;
+ let Inst{24-20} = lumop.Value;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = width.Value;
+ let Inst{11-7} = vd;
+ let Opcode = OPC_LOAD_FP.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+class RVInstVLS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+ dag outs, dag ins, string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> rs2;
+ bits<5> rs1;
+ bits<5> vd;
+ bit vm;
+
+ let Inst{31-29} = nf;
+ let Inst{28-26} = mop.Value;
+ let Inst{25} = vm;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = width.Value;
+ let Inst{11-7} = vd;
+ let Opcode = OPC_LOAD_FP.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+class RVInstVLX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+ dag outs, dag ins, string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> vs2;
+ bits<5> rs1;
+ bits<5> vd;
+ bit vm;
+
+ let Inst{31-29} = nf;
+ let Inst{28-26} = mop.Value;
+ let Inst{25} = vm;
+ let Inst{24-20} = vs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = width.Value;
+ let Inst{11-7} = vd;
+ let Opcode = OPC_LOAD_FP.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+class RVInstVSU<bits<3> nf, RISCVMOP mop, RISCVLSUMOP sumop,
+ RISCVWidth width, dag outs, dag ins, string opcodestr,
+ string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> rs1;
+ bits<5> vs3;
+ bit vm;
+
+ let Inst{31-29} = nf;
+ let Inst{28-26} = mop.Value;
+ let Inst{25} = vm;
+ let Inst{24-20} = sumop.Value;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = width.Value;
+ let Inst{11-7} = vs3;
+ let Opcode = OPC_STORE_FP.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+class RVInstVSS<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+ dag outs, dag ins, string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> rs2;
+ bits<5> rs1;
+ bits<5> vs3;
+ bit vm;
+
+ let Inst{31-29} = nf;
+ let Inst{28-26} = mop.Value;
+ let Inst{25} = vm;
+ let Inst{24-20} = rs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = width.Value;
+ let Inst{11-7} = vs3;
+ let Opcode = OPC_STORE_FP.Value;
+
+ let Uses = [VTYPE, VL];
+}
+
+class RVInstVSX<bits<3> nf, RISCVMOP mop, RISCVWidth width,
+ dag outs, dag ins, string opcodestr, string argstr>
+ : RVInst<outs, ins, opcodestr, argstr, [], InstFormatR> {
+ bits<5> vs2;
+ bits<5> rs1;
+ bits<5> vs3;
+ bit vm;
+
+ let Inst{31-29} = nf;
+ let Inst{28-26} = mop.Value;
+ let Inst{25} = vm;
+ let Inst{24-20} = vs2;
+ let Inst{19-15} = rs1;
+ let Inst{14-12} = width.Value;
+ let Inst{11-7} = vs3;
+ let Opcode = OPC_STORE_FP.Value;
+
+ let Uses = [VTYPE, VL];
+}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
index f1f4e6573df8..21bc508cdc9c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -133,5 +133,24 @@ class RISCVInstrInfo : public RISCVGenInstrInfo {
protected:
const RISCVSubtarget &STI;
};
-}
+
+namespace RISCV {
+// Match with the definitions in RISCVInstrFormatsV.td
+enum RVVConstraintType {
+ NoConstraint = 0,
+ WidenV = 1,
+ WidenW = 2,
+ WidenCvt = 3,
+ Narrow = 4,
+ Iota = 5,
+ SlideUp = 6,
+ Vrgather = 7,
+ Vcompress = 8,
+
+ ConstraintOffset = 5,
+ ConstraintMask = 0b1111
+};
+} // end namespace RISCV
+
+} // end namespace llvm
#endif
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 1f75dd184cf0..b9483062ddeb 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -1177,3 +1177,4 @@ include "RISCVInstrInfoF.td"
include "RISCVInstrInfoD.td"
include "RISCVInstrInfoC.td"
include "RISCVInstrInfoB.td"
+include "RISCVInstrInfoV.td"
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
new file mode 100644
index 000000000000..1c7f53fecb8c
--- /dev/null
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -0,0 +1,873 @@
+//===-- RISCVInstrInfoV.td - RISC-V 'V' instructions -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions from the standard 'V' Vector
+/// extension, version 0.8.
+/// This version is still experimental as the 'V' extension hasn't been
+/// ratified yet.
+///
+//===----------------------------------------------------------------------===//
+
+include "RISCVInstrFormatsV.td"
+
+//===----------------------------------------------------------------------===//
+// Operand and SDNode transformation definitions.
+//===----------------------------------------------------------------------===//
+
+def VTypeIAsmOperand : AsmOperandClass {
+ let Name = "VTypeI";
+ let ParserMethod = "parseVTypeI";
+ let DiagnosticType = "InvalidVTypeI";
+}
+
+def VTypeIOp : Operand<XLenVT> {
+ let ParserMatchClass = VTypeIAsmOperand;
+ let PrintMethod = "printVTypeI";
+ let DecoderMethod = "decodeUImmOperand<11>";
+}
+
+def VRegAsmOperand : AsmOperandClass {
+ let Name = "RVVRegOpOperand";
+ let RenderMethod = "addRegOperands";
+ let PredicateMethod = "isReg";
+ let ParserMethod = "parseRegister";
+}
+
+def VRegOp : RegisterOperand<VR> {
+ let ParserMatchClass = VRegAsmOperand;
+ let PrintMethod = "printOperand";
+}
+
+def VMaskAsmOperand : AsmOperandClass {
+ let Name = "RVVMaskRegOpOperand";
+ let RenderMethod = "addRegOperands";
+ let PredicateMethod = "isV0Reg";
+ let ParserMethod = "parseMaskReg";
+ let IsOptional = 1;
+ let DefaultMethod = "defaultMaskRegOp";
+ let DiagnosticType = "InvalidVMaskRegister";
+}
+
+def VMaskOp : RegisterOperand<VMV0> {
+ let ParserMatchClass = VMaskAsmOperand;
+ let PrintMethod = "printVMaskReg";
+ let EncoderMethod = "getVMaskReg";
+ let DecoderMethod = "decodeVMaskReg";
+}
+
+def simm5 : Operand<XLenVT>, ImmLeaf<XLenVT, [{return isInt<5>(Imm);}]> {
+ let ParserMatchClass = SImmAsmOperand<5>;
+ let EncoderMethod = "getImmOpValue";
+ let DecoderMethod = "decodeSImmOperand<5>";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isInt<5>(Imm);
+ return MCOp.isBareSymbolRef();
+ }];
+}
+
+def SImm5Plus1AsmOperand : AsmOperandClass {
+ let Name = "SImm5Plus1";
+ let RenderMethod = "addSImm5Plus1Operands";
+ let DiagnosticType = "InvalidSImm5Plus1";
+}
+
+def simm5_plus1 : Operand<XLenVT>, ImmLeaf<XLenVT,
+ [{return isInt<5>(Imm - 1);}]> {
+ let ParserMatchClass = SImm5Plus1AsmOperand;
+ let PrintMethod = "printSImm5Plus1";
+ let MCOperandPredicate = [{
+ int64_t Imm;
+ if (MCOp.evaluateAsConstantImm(Imm))
+ return isInt<5>(Imm - 1);
+ return MCOp.isBareSymbolRef();
+ }];
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction class templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
+// load vd, (rs1), vm
+class VUnitStrideLoad<RISCVMOP mop, RISCVLSUMOP lumop, RISCVWidth width,
+ string opcodestr>
+ : RVInstVLU<0b000, mop, lumop, width, (outs VRegOp:$vd),
+ (ins GPR:$rs1, VMaskOp:$vm), opcodestr, "$vd, (${rs1})$vm">;
+
+// load vd, (rs1), rs2, vm
+class VStridedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
+ : RVInstVLS<0b000, mop, width, (outs VRegOp:$vd),
+ (ins GPR:$rs1, GPR:$rs2, VMaskOp:$vm), opcodestr,
+ "$vd, (${rs1}), $rs2$vm">;
+
+// load vd, (rs1), vs2, vm
+class VIndexedLoad<RISCVMOP mop, RISCVWidth width, string opcodestr>
+ : RVInstVLX<0b000, mop, width, (outs VRegOp:$vd),
+ (ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm), opcodestr,
+ "$vd, (${rs1}), $vs2$vm">;
+
+// vl<nf>r.v vd, (rs1)
+class VWholeLoad<bits<3> nf, string opcodestr>
+ : RVInstVLU<nf, MOPLDUnitStrideU, LUMOPUnitStrideWholeReg,
+ LSWidthVSEW, (outs VRegOp:$vd), (ins GPR:$rs1),
+ opcodestr, "$vd, (${rs1})"> {
+ let vm = 1;
+ let Uses = [];
+}
+} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+// store vd, vs3, (rs1), vm
+class VUnitStrideStore<RISCVMOP mop, RISCVLSUMOP sumop, RISCVWidth width,
+ string opcodestr>
+ : RVInstVSU<0b000, mop, sumop, width, (outs),
+ (ins VRegOp:$vs3, GPR:$rs1, VMaskOp:$vm), opcodestr,
+ "$vs3, (${rs1})$vm">;
+
+// store vd, vs3, (rs1), rs2, vm
+class VStridedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
+ : RVInstVSS<0b000, mop, width, (outs),
+ (ins VRegOp:$vs3, GPR:$rs1, GPR:$rs2, VMaskOp:$vm),
+ opcodestr, "$vs3, (${rs1}), $rs2$vm">;
+
+// store vd, vs3, (rs1), vs2, vm
+class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
+ : RVInstVSX<0b000, mop, width, (outs),
+ (ins VRegOp:$vs3, GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
+ opcodestr, "$vs3, (${rs1}), $vs2$vm">;
+
+// vs<nf>r.v vd, (rs1)
+class VWholeStore<bits<3> nf, string opcodestr>
+ : RVInstVSU<nf, MOPSTUnitStride, SUMOPUnitStrideWholeReg,
+ LSWidthVSEW, (outs), (ins VRegOp:$vs3, GPR:$rs1),
+ opcodestr, "$vs3, (${rs1})"> {
+ let vm = 1;
+ let Uses = [];
+}
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// op vd, vs2, vs1, vm
+class VALUVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVV<funct6, opv, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2, VRegOp:$vs1, VMaskOp:$vm),
+ opcodestr, "$vd, $vs2, $vs1$vm">;
+
+// op vd, vs2, vs1, v0 (without mask, use v0 as carry input)
+class VALUmVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVV<funct6, opv, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2, VRegOp:$vs1, VMV0:$v0),
+ opcodestr, "$vd, $vs2, $vs1, v0"> {
+ let vm = 0;
+}
+
+// op vd, vs1, vs2, vm (reverse the order of vs1 and vs2)
+class VALUrVV<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVV<funct6, opv, (outs VRegOp:$vd),
+ (ins VRegOp:$vs1, VRegOp:$vs2, VMaskOp:$vm),
+ opcodestr, "$vd, $vs1, $vs2$vm">;
+
+// op vd, vs1, vs2
+class VALUVVNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVV<funct6, opv, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2, VRegOp:$vs1),
+ opcodestr, "$vd, $vs2, $vs1"> {
+ let vm = 1;
+}
+
+// op vd, vs2, rs1, vm
+class VALUVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVX<funct6, opv, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2, GPR:$rs1, VMaskOp:$vm),
+ opcodestr, "$vd, $vs2, $rs1$vm">;
+
+// op vd, vs2, rs1, v0 (without mask, use v0 as carry input)
+class VALUmVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVX<funct6, opv, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2, GPR:$rs1, VMV0:$v0),
+ opcodestr, "$vd, $vs2, $rs1, v0"> {
+ let vm = 0;
+}
+
+// op vd, rs1, vs2, vm (reverse the order of rs1 and vs2)
+class VALUrVX<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVX<funct6, opv, (outs VRegOp:$vd),
+ (ins GPR:$rs1, VRegOp:$vs2, VMaskOp:$vm),
+ opcodestr, "$vd, $rs1, $vs2$vm">;
+
+// op vd, vs1, vs2
+class VALUVXNoVm<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVX<funct6, opv, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2, GPR:$rs1),
+ opcodestr, "$vd, $vs2, $rs1"> {
+ let vm = 1;
+}
+
+// op vd, vs2, imm, vm
+class VALUVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
+ : RVInstIVI<funct6, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2, optype:$imm, VMaskOp:$vm),
+ opcodestr, "$vd, $vs2, $imm$vm">;
+
+// op vd, vs2, imm, v0 (without mask, use v0 as carry input)
+class VALUmVI<bits<6> funct6, string opcodestr, Operand optype = simm5>
+ : RVInstIVI<funct6, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2, optype:$imm, VMV0:$v0),
+ opcodestr, "$vd, $vs2, $imm, v0"> {
+ let vm = 0;
+}
+
+// op vd, vs2, imm, vm
+class VALUVINoVm<bits<6> funct6, string opcodestr, Operand optype = simm5>
+ : RVInstIVI<funct6, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2, optype:$imm),
+ opcodestr, "$vd, $vs2, $imm"> {
+ let vm = 1;
+}
+
+// op vd, vs2, rs1, vm (Float)
+class VALUVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVX<funct6, opv, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2, FPR32:$rs1, VMaskOp:$vm),
+ opcodestr, "$vd, $vs2, $rs1$vm">;
+
+// op vd, rs1, vs2, vm (Float) (with mask, reverse the order of rs1 and vs2)
+class VALUrVF<bits<6> funct6, RISCVVFormat opv, string opcodestr>
+ : RVInstVX<funct6, opv, (outs VRegOp:$vd),
+ (ins FPR32:$rs1, VRegOp:$vs2, VMaskOp:$vm),
+ opcodestr, "$vd, $rs1, $vs2$vm">;
+
+// op vd, vs2, vm (use vs1 as instruction encoding)
+class VALUVs2<bits<6> funct6, bits<5> vs1, RISCVVFormat opv, string opcodestr>
+ : RVInstV<funct6, vs1, opv, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2, VMaskOp:$vm),
+ opcodestr, "$vd, $vs2$vm">;
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+//===----------------------------------------------------------------------===//
+// Combination of instruction classes.
+// Use these multiclasses to define instructions more easily.
+//===----------------------------------------------------------------------===//
+multiclass VALU_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
+ def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">;
+ def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
+ def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>;
+}
+
+multiclass VALU_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+ def V : VALUVV<funct6, OPIVV, opcodestr # "." # vw # "v">;
+ def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALUr_IV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+ def V : VALUrVV<funct6, OPIVV, opcodestr # "." # vw # "v">;
+ def X : VALUrVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALU_IV_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5, string vw = "v"> {
+ def X : VALUVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
+ def I : VALUVI<funct6, opcodestr # "." # vw # "i", optype>;
+}
+
+multiclass VALU_IV_V<string opcodestr, bits<6> funct6> {
+ def _VS : VALUVV<funct6, OPIVV, opcodestr # ".vs">;
+}
+
+multiclass VALUr_IV_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+ def X : VALUrVX<funct6, OPIVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALU_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+ def V : VALUVV<funct6, OPMVV, opcodestr # "." # vw # "v">;
+ def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALU_MV_V<string opcodestr, bits<6> funct6> {
+ def _VS : VALUVV<funct6, OPMVV, opcodestr # ".vs">;
+}
+
+multiclass VALU_MV_Mask<string opcodestr, bits<6> funct6, string vm = "v"> {
+ def M : VALUVVNoVm<funct6, OPMVV, opcodestr # "." # vm # "m">;
+}
+
+multiclass VALU_MV_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+ def X : VALUVX<funct6, OPMVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALUr_MV_V_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+ def V : VALUrVV<funct6, OPMVV, opcodestr # "." # vw # "v">;
+ def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALUr_MV_X<string opcodestr, bits<6> funct6, string vw = "v"> {
+ def X : VALUrVX<funct6, OPMVX, opcodestr # "." # vw # "x">;
+}
+
+multiclass VALU_MV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
+ def "" : VALUVs2<funct6, vs1, OPMVV, opcodestr>;
+}
+
+multiclass VALUm_IV_V_X_I<string opcodestr, bits<6> funct6> {
+ def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">;
+ def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">;
+ def IM : VALUmVI<funct6, opcodestr # ".vim">;
+}
+
+multiclass VALUm_IV_V_X<string opcodestr, bits<6> funct6> {
+ def VM : VALUmVV<funct6, OPIVV, opcodestr # ".vvm">;
+ def XM : VALUmVX<funct6, OPIVX, opcodestr # ".vxm">;
+}
+
+multiclass VALUNoVm_IV_V_X_I<string opcodestr, bits<6> funct6, Operand optype = simm5> {
+ def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">;
+ def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">;
+ def I : VALUVINoVm<funct6, opcodestr # ".vi", optype>;
+}
+
+multiclass VALUNoVm_IV_V_X<string opcodestr, bits<6> funct6> {
+ def V : VALUVVNoVm<funct6, OPIVV, opcodestr # ".vv">;
+ def X : VALUVXNoVm<funct6, OPIVX, opcodestr # ".vx">;
+}
+
+multiclass VALU_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
+ def V : VALUVV<funct6, OPFVV, opcodestr # "." # vw # "v">;
+ def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+}
+
+multiclass VALU_FV_F<string opcodestr, bits<6> funct6, string vw = "v"> {
+ def F : VALUVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+}
+
+multiclass VALUr_FV_V_F<string opcodestr, bits<6> funct6, string vw = "v"> {
+ def V : VALUrVV<funct6, OPFVV, opcodestr # "." # vw # "v">;
+ def F : VALUrVF<funct6, OPFVF, opcodestr # "." # vw # "f">;
+}
+
+multiclass VALU_FV_V<string opcodestr, bits<6> funct6> {
+ def _VS : VALUVV<funct6, OPFVV, opcodestr # ".vs">;
+}
+
+multiclass VALU_FV_VS2<string opcodestr, bits<6> funct6, bits<5> vs1> {
+ def "" : VALUVs2<funct6, vs1, OPFVV, opcodestr>;
+}
+
+//===----------------------------------------------------------------------===//
+// Instructions
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtV] in {
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
+def VSETVLI : RVInstSetVLi<(outs GPR:$rd), (ins GPR:$rs1, VTypeIOp:$vtypei),
+ "vsetvli", "$rd, $rs1, $vtypei">;
+
+def VSETVL : RVInstSetVL<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+ "vsetvl", "$rd, $rs1, $rs2">;
+} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
+
+// Vector Unit-Stride Instructions
+def VLB_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVByte, "vlb.v">;
+def VLH_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVHalf, "vlh.v">;
+def VLW_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStride, LSWidthVWord, "vlw.v">;
+
+def VLBU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVByte, "vlbu.v">;
+def VLHU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVHalf, "vlhu.v">;
+def VLWU_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVWord, "vlwu.v">;
+
+def VLE_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStride, LSWidthVSEW, "vle.v">;
+
+def VLBFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVByte, "vlbff.v">;
+def VLHFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVHalf, "vlhff.v">;
+def VLWFF_V : VUnitStrideLoad<MOPLDUnitStrideS, LUMOPUnitStrideFF, LSWidthVWord, "vlwff.v">;
+
+def VLBUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVByte, "vlbuff.v">;
+def VLHUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVHalf, "vlhuff.v">;
+def VLWUFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVWord, "vlwuff.v">;
+
+def VLEFF_V : VUnitStrideLoad<MOPLDUnitStrideU, LUMOPUnitStrideFF, LSWidthVSEW, "vleff.v">;
+
+def VSB_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVByte, "vsb.v">;
+def VSH_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVHalf, "vsh.v">;
+def VSW_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVWord, "vsw.v">;
+
+def VSE_V : VUnitStrideStore<MOPSTUnitStride, SUMOPUnitStride, LSWidthVSEW, "vse.v">;
+
+// Vector Strided Instructions
+def VLSB_V : VStridedLoad<MOPLDStridedS, LSWidthVByte, "vlsb.v">;
+def VLSH_V : VStridedLoad<MOPLDStridedS, LSWidthVHalf, "vlsh.v">;
+def VLSW_V : VStridedLoad<MOPLDStridedS, LSWidthVWord, "vlsw.v">;
+
+def VLSBU_V : VStridedLoad<MOPLDStridedU, LSWidthVByte, "vlsbu.v">;
+def VLSHU_V : VStridedLoad<MOPLDStridedU, LSWidthVHalf, "vlshu.v">;
+def VLSWU_V : VStridedLoad<MOPLDStridedU, LSWidthVWord, "vlswu.v">;
+
+def VLSE_V : VStridedLoad<MOPLDStridedU, LSWidthVSEW, "vlse.v">;
+
+def VSSB_V : VStridedStore<MOPSTStrided, LSWidthVByte, "vssb.v">;
+def VSSH_V : VStridedStore<MOPSTStrided, LSWidthVHalf, "vssh.v">;
+def VSSW_V : VStridedStore<MOPSTStrided, LSWidthVWord, "vssw.v">;
+def VSSE_V : VStridedStore<MOPSTStrided, LSWidthVSEW, "vsse.v">;
+
+// Vector Indexed Instructions
+def VLXB_V : VIndexedLoad<MOPLDIndexedS, LSWidthVByte, "vlxb.v">;
+def VLXH_V : VIndexedLoad<MOPLDIndexedS, LSWidthVHalf, "vlxh.v">;
+def VLXW_V : VIndexedLoad<MOPLDIndexedS, LSWidthVWord, "vlxw.v">;
+
+def VLXBU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVByte, "vlxbu.v">;
+def VLXHU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVHalf, "vlxhu.v">;
+def VLXWU_V : VIndexedLoad<MOPLDIndexedU, LSWidthVWord, "vlxwu.v">;
+
+def VLXE_V : VIndexedLoad<MOPLDIndexedU, LSWidthVSEW, "vlxe.v">;
+
+def VSXB_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVByte, "vsxb.v">;
+def VSXH_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVHalf, "vsxh.v">;
+def VSXW_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVWord, "vsxw.v">;
+def VSXE_V : VIndexedStore<MOPSTIndexedOrder, LSWidthVSEW, "vsxe.v">;
+
+def VSUXB_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVByte, "vsuxb.v">;
+def VSUXH_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVHalf, "vsuxh.v">;
+def VSUXW_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVWord, "vsuxw.v">;
+def VSUXE_V : VIndexedStore<MOPSTIndexedUnOrd, LSWidthVSEW, "vsuxe.v">;
+
+def VL1R_V : VWholeLoad<0, "vl1r.v">;
+def VS1R_V : VWholeStore<0, "vs1r.v">;
+
+// Vector Single-Width Integer Add and Subtract
+defm VADD_V : VALU_IV_V_X_I<"vadd", 0b000000>;
+defm VSUB_V : VALU_IV_V_X<"vsub", 0b000010>;
+defm VRSUB_V : VALU_IV_X_I<"vrsub", 0b000011>;
+
+// Vector Widening Integer Add/Subtract
+// Refer to 11.2 Widening Vector Arithmetic Instructions
+// The destination vector register group cannot overlap a source vector
+// register group of a
diff erent element width (including the mask register
+// if masked), otherwise an illegal instruction exception is raised.
+let Constraints = "@earlyclobber $vd" in {
+let RVVConstraint = WidenV in {
+defm VWADDU_V : VALU_MV_V_X<"vwaddu", 0b110000>;
+defm VWSUBU_V : VALU_MV_V_X<"vwsubu", 0b110010>;
+defm VWADD_V : VALU_MV_V_X<"vwadd", 0b110001>;
+defm VWSUB_V : VALU_MV_V_X<"vwsub", 0b110011>;
+} // RVVConstraint = WidenV
+// Set earlyclobber for following instructions for second and mask operands.
+// This has the downside that the earlyclobber constraint is too coarse and
+// will impose unnecessary restrictions by not allowing the destination to
+// overlap with the first (wide) operand.
+let RVVConstraint = WidenW in {
+defm VWADDU_W : VALU_MV_V_X<"vwaddu", 0b110100, "w">;
+defm VWSUBU_W : VALU_MV_V_X<"vwsubu", 0b110110, "w">;
+defm VWADD_W : VALU_MV_V_X<"vwadd", 0b110101, "w">;
+defm VWSUB_W : VALU_MV_V_X<"vwsub", 0b110111, "w">;
+} // RVVConstraint = WidenW
+} // Constraints = "@earlyclobber $vd"
+
+def : InstAlias<"vwcvt.x.x.v $vd, $vs$vm",
+ (VWADD_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>;
+def : InstAlias<"vwcvtu.x.x.v $vd, $vs$vm",
+ (VWADDU_VX VRegOp:$vd, VRegOp:$vs, X0, VMaskOp:$vm)>;
+
+// Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
+defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>;
+defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>;
+defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>;
+defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>;
+defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>;
+defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>;
+
+// Vector Bitwise Logical Instructions
+defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>;
+defm VOR_V : VALU_IV_V_X_I<"vor", 0b001010>;
+defm VXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>;
+
+def : InstAlias<"vnot.v $vd, $vs$vm",
+ (VXOR_VI VRegOp:$vd, VRegOp:$vs, -1, VMaskOp:$vm)>;
+
+// Vector Single-Width Bit Shift Instructions
+defm VSLL_V : VALU_IV_V_X_I<"vsll", 0b100101, uimm5>;
+defm VSRL_V : VALU_IV_V_X_I<"vsrl", 0b101000, uimm5>;
+defm VSRA_V : VALU_IV_V_X_I<"vsra", 0b101001, uimm5>;
+
+// Vector Narrowing Integer Right Shift Instructions
+// Refer to 11.3. Narrowing Vector Arithmetic Instructions
+// The destination vector register group cannot overlap the first source
+// vector register group (specified by vs2). The destination vector register
+// group cannot overlap the mask register if used, unless LMUL=1.
+let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in {
+defm VNSRL_W : VALU_IV_V_X_I<"vnsrl", 0b101100, uimm5, "w">;
+defm VNSRA_W : VALU_IV_V_X_I<"vnsra", 0b101101, uimm5, "w">;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
+
+// Vector Integer Comparison Instructions
+defm VMSEQ_V : VALU_IV_V_X_I<"vmseq", 0b011000>;
+defm VMSNE_V : VALU_IV_V_X_I<"vmsne", 0b011001>;
+defm VMSLTU_V : VALU_IV_V_X<"vmsltu", 0b011010>;
+defm VMSLT_V : VALU_IV_V_X<"vmslt", 0b011011>;
+defm VMSLEU_V : VALU_IV_V_X_I<"vmsleu", 0b011100>;
+defm VMSLE_V : VALU_IV_V_X_I<"vmsle", 0b011101>;
+defm VMSGTU_V : VALU_IV_X_I<"vmsgtu", 0b011110>;
+defm VMSGT_V : VALU_IV_X_I<"vmsgt", 0b011111>;
+
+def : InstAlias<"vmsgtu.vv $vd, $va, $vb$vm",
+ (VMSLTU_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
+def : InstAlias<"vmsgt.vv $vd, $va, $vb$vm",
+ (VMSLT_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
+def : InstAlias<"vmsgeu.vv $vd, $va, $vb$vm",
+ (VMSLEU_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
+def : InstAlias<"vmsge.vv $vd, $va, $vb$vm",
+ (VMSLE_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
+def : InstAlias<"vmsltu.vi $vd, $va, $imm$vm",
+ (VMSLEU_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm,
+ VMaskOp:$vm), 0>;
+def : InstAlias<"vmslt.vi $vd, $va, $imm$vm",
+ (VMSLE_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm,
+ VMaskOp:$vm), 0>;
+def : InstAlias<"vmsgeu.vi $vd, $va, $imm$vm",
+ (VMSGTU_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm,
+ VMaskOp:$vm), 0>;
+def : InstAlias<"vmsge.vi $vd, $va, $imm$vm",
+ (VMSGT_VI VRegOp:$vd, VRegOp:$va, simm5_plus1:$imm,
+ VMaskOp:$vm), 0>;
+
+// Vector Integer Min/Max Instructions
+defm VMINU_V : VALU_IV_V_X<"vminu", 0b000100>;
+defm VMIN_V : VALU_IV_V_X<"vmin", 0b000101>;
+defm VMAXU_V : VALU_IV_V_X<"vmaxu", 0b000110>;
+defm VMAX_V : VALU_IV_V_X<"vmax", 0b000111>;
+
+// Vector Single-Width Integer Multiply Instructions
+defm VMUL_V : VALU_MV_V_X<"vmul", 0b100101>;
+defm VMULH_V : VALU_MV_V_X<"vmulh", 0b100111>;
+defm VMULHU_V : VALU_MV_V_X<"vmulhu", 0b100100>;
+defm VMULHSU_V : VALU_MV_V_X<"vmulhsu", 0b100110>;
+
+// Vector Integer Divide Instructions
+defm VDIVU_V : VALU_MV_V_X<"vdivu", 0b100000>;
+defm VDIV_V : VALU_MV_V_X<"vdiv", 0b100001>;
+defm VREMU_V : VALU_MV_V_X<"vremu", 0b100010>;
+defm VREM_V : VALU_MV_V_X<"vrem", 0b100011>;
+
+// Vector Widening Integer Multiply Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
+defm VWMUL_V : VALU_MV_V_X<"vwmul", 0b111011>;
+defm VWMULU_V : VALU_MV_V_X<"vwmulu", 0b111000>;
+defm VWMULSU_V : VALU_MV_V_X<"vwmulsu", 0b111010>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+
+// Vector Single-Width Integer Multiply-Add Instructions
+defm VMACC_V : VALUr_MV_V_X<"vmacc", 0b101101>;
+defm VNMSAC_V : VALUr_MV_V_X<"vnmsac", 0b101111>;
+defm VMADD_V : VALUr_MV_V_X<"vmadd", 0b101001>;
+defm VNMSUB_V : VALUr_MV_V_X<"vnmsub", 0b101011>;
+
+// Vector Widening Integer Multiply-Add Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
+defm VWMACCU_V : VALUr_MV_V_X<"vwmaccu", 0b111100>;
+defm VWMACC_V : VALUr_MV_V_X<"vwmacc", 0b111101>;
+defm VWMACCSU_V : VALUr_MV_V_X<"vwmaccsu", 0b111111>;
+defm VWMACCUS_V : VALUr_MV_X<"vwmaccus", 0b111110>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+
+// Vector Integer Merge Instructions
+defm VMERGE_V : VALUm_IV_V_X_I<"vmerge", 0b010111>;
+
+// Vector Integer Move Instructions
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vs2 = 0, vm = 1 in {
+// op vd, vs1
+def VMV_V_V : RVInstVV<0b010111, OPIVV, (outs VRegOp:$vd),
+ (ins VRegOp:$vs1), "vmv.v.v", "$vd, $vs1">;
+// op vd, rs1
+def VMV_V_X : RVInstVX<0b010111, OPIVX, (outs VRegOp:$vd),
+ (ins GPR:$rs1), "vmv.v.x", "$vd, $rs1">;
+// op vd, imm
+def VMV_V_I : RVInstIVI<0b010111, (outs VRegOp:$vd),
+ (ins simm5:$imm), "vmv.v.i", "$vd, $imm">;
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+// Vector Fixed-Point Arithmetic Instructions
+defm VSADDU_V : VALU_IV_V_X_I<"vsaddu", 0b100000>;
+defm VSADD_V : VALU_IV_V_X_I<"vsadd", 0b100001>;
+defm VSSUBU_V : VALU_IV_V_X<"vssubu", 0b100010>;
+defm VSSUB_V : VALU_IV_V_X<"vssub", 0b100011>;
+
+// Vector Single-Width Averaging Add and Subtract
+defm VAADDU_V : VALU_MV_V_X<"vaaddu", 0b001000>;
+defm VAADD_V : VALU_MV_V_X<"vaadd", 0b001001>;
+defm VASUBU_V : VALU_MV_V_X<"vasubu", 0b001010>;
+defm VASUB_V : VALU_MV_V_X<"vasub", 0b001011>;
+
+// Vector Single-Width Fractional Multiply with Rounding and Saturation
+defm VSMUL_V : VALU_IV_V_X<"vsmul", 0b100111>;
+
+// Vector Single-Width Scaling Shift Instructions
+defm VSSRL_V : VALU_IV_V_X_I<"vssrl", 0b101010, uimm5>;
+defm VSSRA_V : VALU_IV_V_X_I<"vssra", 0b101011, uimm5>;
+
+// Vector Narrowing Fixed-Point Clip Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in {
+defm VNCLIPU_W : VALU_IV_V_X_I<"vnclipu", 0b101110, uimm5, "w">;
+defm VNCLIP_W : VALU_IV_V_X_I<"vnclip", 0b101111, uimm5, "w">;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
+
+// Vector Single-Width Floating-Point Add/Subtract Instructions
+defm VFADD_V : VALU_FV_V_F<"vfadd", 0b000000>;
+defm VFSUB_V : VALU_FV_V_F<"vfsub", 0b000010>;
+defm VFRSUB_V : VALU_FV_F<"vfrsub", 0b100111>;
+
+// Vector Widening Floating-Point Add/Subtract Instructions
+let Constraints = "@earlyclobber $vd" in {
+let RVVConstraint = WidenV in {
+defm VFWADD_V : VALU_FV_V_F<"vfwadd", 0b110000>;
+defm VFWSUB_V : VALU_FV_V_F<"vfwsub", 0b110010>;
+} // RVVConstraint = WidenV
+// Set earlyclobber for following instructions for second and mask operands.
+// This has the downside that the earlyclobber constraint is too coarse and
+// will impose unnecessary restrictions by not allowing the destination to
+// overlap with the first (wide) operand.
+let RVVConstraint = WidenW in {
+defm VFWADD_W : VALU_FV_V_F<"vfwadd", 0b110100, "w">;
+defm VFWSUB_W : VALU_FV_V_F<"vfwsub", 0b110110, "w">;
+} // RVVConstraint = WidenW
+} // Constraints = "@earlyclobber $vd"
+
+// Vector Single-Width Floating-Point Multiply/Divide Instructions
+defm VFMUL_V : VALU_FV_V_F<"vfmul", 0b100100>;
+defm VFDIV_V : VALU_FV_V_F<"vfdiv", 0b100000>;
+defm VFRDIV_V : VALU_FV_F<"vfrdiv", 0b100001>;
+
+// Vector Widening Floating-Point Multiply
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
+defm VFWMUL_V : VALU_FV_V_F<"vfwmul", 0b111000>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+
+// Vector Single-Width Floating-Point Fused Multiply-Add Instructions
+defm VFMACC_V : VALUr_FV_V_F<"vfmacc", 0b101100>;
+defm VFNMACC_V : VALUr_FV_V_F<"vfnmacc", 0b101101>;
+defm VFMSAC_V : VALUr_FV_V_F<"vfmsac", 0b101110>;
+defm VFNMSAC_V : VALUr_FV_V_F<"vfnmsac", 0b101111>;
+defm VFMADD_V : VALUr_FV_V_F<"vfmadd", 0b101000>;
+defm VFNMADD_V : VALUr_FV_V_F<"vfnmadd", 0b101001>;
+defm VFMSUB_V : VALUr_FV_V_F<"vfmsub", 0b101010>;
+defm VFNMSUB_V : VALUr_FV_V_F<"vfnmsub", 0b101011>;
+
+// Vector Widening Floating-Point Fused Multiply-Add Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
+defm VFWMACC_V : VALUr_FV_V_F<"vfwmacc", 0b111100>;
+defm VFWNMACC_V : VALUr_FV_V_F<"vfwnmacc", 0b111101>;
+defm VFWMSAC_V : VALUr_FV_V_F<"vfwmsac", 0b111110>;
+defm VFWNMSAC_V : VALUr_FV_V_F<"vfwnmsac", 0b111111>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
+
+// Vector Floating-Point Square-Root Instruction
+defm VFSQRT_V : VALU_FV_VS2<"vfsqrt.v", 0b100011, 0b00000>;
+
+// Vector Floating-Point MIN/MAX Instructions
+defm VFMIN_V : VALU_FV_V_F<"vfmin", 0b000100>;
+defm VFMAX_V : VALU_FV_V_F<"vfmax", 0b000110>;
+
+// Vector Floating-Point Sign-Injection Instructions
+defm VFSGNJ_V : VALU_FV_V_F<"vfsgnj", 0b001000>;
+defm VFSGNJN_V : VALU_FV_V_F<"vfsgnjn", 0b001001>;
+defm VFSGNJX_V : VALU_FV_V_F<"vfsgnjx", 0b001010>;
+
+// Vector Floating-Point Compare Instructions
+defm VMFEQ_V : VALU_FV_V_F<"vmfeq", 0b011000>;
+defm VMFNE_V : VALU_FV_V_F<"vmfne", 0b011100>;
+defm VMFLT_V : VALU_FV_V_F<"vmflt", 0b011011>;
+defm VMFLE_V : VALU_FV_V_F<"vmfle", 0b011001>;
+defm VMFGT_V : VALU_FV_F<"vmfgt", 0b011101>;
+defm VMFGE_V : VALU_FV_F<"vmfge", 0b011111>;
+
+def : InstAlias<"vmfgt.vv $vd, $va, $vb$vm",
+ (VMFLT_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
+def : InstAlias<"vmfge.vv $vd, $va, $vb$vm",
+ (VMFLE_VV VRegOp:$vd, VRegOp:$vb, VRegOp:$va, VMaskOp:$vm), 0>;
+
+// Vector Floating-Point Classify Instruction
+defm VFCLASS_V : VALU_FV_VS2<"vfclass.v", 0b100011, 0b10000>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// Vector Floating-Point Merge Instruction
+def VFMERGE_VFM : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2, FPR32:$rs1, VMV0:$v0),
+ "vfmerge.vfm", "$vd, $vs2, $rs1, v0"> {
+ let vm = 0;
+}
+
+// Vector Floating-Point Move Instruction
+def VFMV_V_F : RVInstVX<0b010111, OPFVF, (outs VRegOp:$vd),
+ (ins FPR32:$rs1), "vfmv.v.f", "$vd, $rs1"> {
+ let vs2 = 0;
+ let vm = 1;
+}
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+// Single-Width Floating-Point/Integer Type-Convert Instructions
+defm VFCVT_XU_F_V : VALU_FV_VS2<"vfcvt.xu.f.v", 0b100010, 0b00000>;
+defm VFCVT_X_F_V : VALU_FV_VS2<"vfcvt.x.f.v", 0b100010, 0b00001>;
+defm VFCVT_F_XU_V : VALU_FV_VS2<"vfcvt.f.xu.v", 0b100010, 0b00010>;
+defm VFCVT_F_X_V : VALU_FV_VS2<"vfcvt.f.x.v", 0b100010, 0b00011>;
+
+// Widening Floating-Point/Integer Type-Convert Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt in {
+defm VFWCVT_XU_F_V : VALU_FV_VS2<"vfwcvt.xu.f.v", 0b100010, 0b01000>;
+defm VFWCVT_X_F_V : VALU_FV_VS2<"vfwcvt.x.f.v", 0b100010, 0b01001>;
+defm VFWCVT_F_XU_V : VALU_FV_VS2<"vfwcvt.f.xu.v", 0b100010, 0b01010>;
+defm VFWCVT_F_X_V : VALU_FV_VS2<"vfwcvt.f.x.v", 0b100010, 0b01011>;
+defm VFWCVT_F_F_V : VALU_FV_VS2<"vfwcvt.f.f.v", 0b100010, 0b01100>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = WidenCvt
+
+// Narrowing Floating-Point/Integer Type-Convert Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = Narrow in {
+defm VFNCVT_XU_F_W : VALU_FV_VS2<"vfncvt.xu.f.w", 0b100010, 0b10000>;
+defm VFNCVT_X_F_W : VALU_FV_VS2<"vfncvt.x.f.w", 0b100010, 0b10001>;
+defm VFNCVT_F_XU_W : VALU_FV_VS2<"vfncvt.f.xu.w", 0b100010, 0b10010>;
+defm VFNCVT_F_X_W : VALU_FV_VS2<"vfncvt.f.x.w", 0b100010, 0b10011>;
+defm VFNCVT_F_F_W : VALU_FV_VS2<"vfncvt.f.f.w", 0b100010, 0b10100>;
+defm VFNCVT_ROD_F_F_W : VALU_FV_VS2<"vfncvt.rod.f.f.w", 0b100010, 0b10101>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Narrow
+
+// Vector Single-Width Integer Reduction Instructions
+defm VREDSUM : VALU_MV_V<"vredsum", 0b000000>;
+defm VREDMAXU : VALU_MV_V<"vredmaxu", 0b000110>;
+defm VREDMAX : VALU_MV_V<"vredmax", 0b000111>;
+defm VREDMINU : VALU_MV_V<"vredminu", 0b000100>;
+defm VREDMIN : VALU_MV_V<"vredmin", 0b000101>;
+defm VREDAND : VALU_MV_V<"vredand", 0b000001>;
+defm VREDOR : VALU_MV_V<"vredor", 0b000010>;
+defm VREDXOR : VALU_MV_V<"vredxor", 0b000011>;
+
+// Vector Widening Integer Reduction Instructions
+let Constraints = "@earlyclobber $vd" in {
+// Set earlyclobber for following instructions for second and mask operands.
+// This has the downside that the earlyclobber constraint is too coarse and
+// will impose unnecessary restrictions by not allowing the destination to
+// overlap with the first (wide) operand.
+defm VWREDSUMU : VALU_IV_V<"vwredsumu", 0b110000>;
+defm VWREDSUM : VALU_IV_V<"vwredsum", 0b110001>;
+} // Constraints = "@earlyclobber $vd"
+
+// Vector Single-Width Floating-Point Reduction Instructions
+defm VFREDOSUM : VALU_FV_V<"vfredosum", 0b000011>;
+defm VFREDSUM : VALU_FV_V<"vfredsum", 0b000001>;
+defm VFREDMAX : VALU_FV_V<"vfredmax", 0b000111>;
+defm VFREDMIN : VALU_FV_V<"vfredmin", 0b000101>;
+
+// Vector Widening Floating-Point Reduction Instructions
+let Constraints = "@earlyclobber $vd" in {
+// Set earlyclobber for following instructions for second and mask operands.
+// This has the downside that the earlyclobber constraint is too coarse and
+// will impose unnecessary restrictions by not allowing the destination to
+// overlap with the first (wide) operand.
+defm VFWREDOSUM : VALU_FV_V<"vfwredosum", 0b110011>;
+defm VFWREDSUM : VALU_FV_V<"vfwredsum", 0b110001>;
+} // Constraints = "@earlyclobber $vd"
+
+// Vector Mask-Register Logical Instructions
+defm VMAND_M : VALU_MV_Mask<"vmand", 0b011001, "m">;
+defm VMNAND_M : VALU_MV_Mask<"vmnand", 0b011101, "m">;
+defm VMANDNOT_M : VALU_MV_Mask<"vmandnot", 0b011000, "m">;
+defm VMXOR_M : VALU_MV_Mask<"vmxor", 0b011011, "m">;
+defm VMOR_M : VALU_MV_Mask<"vmor", 0b011010, "m">;
+defm VMNOR_M : VALU_MV_Mask<"vmnor", 0b011110, "m">;
+defm VMORNOT_M : VALU_MV_Mask<"vmornot", 0b011100, "m">;
+defm VMXNOR_M : VALU_MV_Mask<"vmxnor", 0b011111, "m">;
+
+def : InstAlias<"vmcpy.m $vd, $vs",
+ (VMAND_MM VRegOp:$vd, VRegOp:$vs, VRegOp:$vs)>;
+def : InstAlias<"vmclr.m $vd",
+ (VMXOR_MM VRegOp:$vd, VRegOp:$vd, VRegOp:$vd)>;
+def : InstAlias<"vmset.m $vd",
+ (VMXNOR_MM VRegOp:$vd, VRegOp:$vd, VRegOp:$vd)>;
+def : InstAlias<"vmnot.m $vd, $vs",
+ (VMNAND_MM VRegOp:$vd, VRegOp:$vs, VRegOp:$vs)>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+// Vector mask population count vpopc
+def VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd),
+ (ins VRegOp:$vs2, VMaskOp:$vm),
+ "vpopc.m", "$vd, $vs2$vm">;
+
+// vfirst find-first-set mask bit
+def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd),
+ (ins VRegOp:$vs2, VMaskOp:$vm),
+ "vfirst.m", "$vd, $vs2$vm">;
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+// vmsbf.m set-before-first mask bit
+defm VMSBF_M : VALU_MV_VS2<"vmsbf.m", 0b010100, 0b00001>;
+
+// vmsif.m set-including-first mask bit
+defm VMSIF_M : VALU_MV_VS2<"vmsif.m", 0b010100, 0b00011>;
+
+// vmsof.m set-only-first mask bit
+defm VMSOF_M : VALU_MV_VS2<"vmsof.m", 0b010100, 0b00010>;
+
+// Vector Iota Instruction
+let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in {
+defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Iota
+
+// Vector Element Index Instruction
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VRegOp:$vd),
+ (ins VMaskOp:$vm), "vid.v", "$vd$vm"> {
+ let vs2 = 0;
+}
+
+// Integer Scalar Move Instructions
+let vm = 1 in {
+def VMV_X_S : RVInstV<0b010000, 0b00000, OPMVV, (outs GPR:$vd),
+ (ins VRegOp:$vs2), "vmv.x.s", "$vd, $vs2">;
+def VMV_S_X : RVInstV2<0b010000, 0b00000, OPMVX, (outs VRegOp:$vd),
+ (ins GPR:$rs1), "vmv.s.x", "$vd, $rs1">;
+
+}
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1 in {
+// Floating-Point Scalar Move Instructions
+def VFMV_F_S : RVInstV<0b010000, 0b00000, OPFVV, (outs FPR32:$vd),
+ (ins VRegOp:$vs2), "vfmv.f.s", "$vd, $vs2">;
+def VFMV_S_F : RVInstV2<0b010000, 0b00000, OPFVF, (outs VRegOp:$vd),
+ (ins FPR32:$rs1), "vfmv.s.f", "$vd, $rs1">;
+
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
+
+// Vector Slide Instructions
+let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
+defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
+defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;
+
+let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
+defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
+defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>;
+
+// Vector Register Gather Instruction
+let Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather in {
+defm VRGATHER_V : VALU_IV_V_X_I<"vrgather", 0b001100, uimm5>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Vrgather
+
+// Vector Compress Instruction
+let Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress in {
+defm VCOMPRESS_V : VALU_MV_Mask<"vcompress", 0b010111>;
+} // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
+foreach nf = [1, 2, 4, 8] in {
+ def VMV#nf#R_V : RVInstV<0b100111, !add(nf, -1), OPIVI, (outs VRegOp:$vd),
+ (ins VRegOp:$vs2), "vmv" # nf # "r.v",
+ "$vd, $vs2"> {
+ let Uses = [];
+ let vm = 1;
+ }
+}
+} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
+} // Predicates = [HasStdExtV]
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
index fd234c45ae9c..c3a995dee07f 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
@@ -35,6 +35,8 @@ static_assert(RISCV::F31_F == RISCV::F0_F + 31,
static_assert(RISCV::F1_D == RISCV::F0_D + 1, "Register list not consecutive");
static_assert(RISCV::F31_D == RISCV::F0_D + 31,
"Register list not consecutive");
+static_assert(RISCV::V1 == RISCV::V0 + 1, "Register list not consecutive");
+static_assert(RISCV::V31 == RISCV::V0 + 31, "Register list not consecutive");
RISCVRegisterInfo::RISCVRegisterInfo(unsigned HwMode)
: RISCVGenRegisterInfo(RISCV::X1, /*DwarfFlavour*/0, /*EHFlavor*/0,
diff --git a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
index 82b37afd0805..7544b4b3b845 100644
--- a/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVRegisterInfo.td
@@ -33,7 +33,21 @@ class RISCVReg64<RISCVReg32 subreg> : Register<""> {
let AltNames = subreg.AltNames;
}
+class RISCVRegWithSubRegs<bits<5> Enc, string n, list<Register> subregs,
+ list<string> alt = []>
+ : RegisterWithSubRegs<n, subregs> {
+ let HWEncoding{4-0} = Enc;
+ let AltNames = alt;
+}
+
def ABIRegAltName : RegAltNameIndex;
+
+def sub_vrm2 : SubRegIndex<64, -1>;
+def sub_vrm2_hi : SubRegIndex<64, -1>;
+def sub_vrm4 : SubRegIndex<128, -1>;
+def sub_vrm4_hi : SubRegIndex<128, -1>;
+def sub_vrm8 : SubRegIndex<256, -1>;
+def sub_vrm8_hi : SubRegIndex<256, -1>;
} // Namespace = "RISCV"
// Integer registers
@@ -233,3 +247,88 @@ def FPR64C : RegisterClass<"RISCV", [f64], 64, (add
(sequence "F%u_D", 10, 15),
(sequence "F%u_D", 8, 9)
)>;
+
+// Vector registers
+let RegAltNameIndices = [ABIRegAltName] in {
+ foreach Index = 0-31 in {
+ def V#Index : RISCVReg<Index, "v"#Index, ["v"#Index]>, DwarfRegNum<[!add(Index, 64)]>;
+ }
+
+ foreach Index = [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22,
+ 24, 26, 28, 30] in {
+ def V#Index#M2 : RISCVRegWithSubRegs<Index, "v"#Index,
+ [!cast<Register>("V"#Index),
+ !cast<Register>("V"#!add(Index, 1))],
+ ["v"#Index]>,
+ DwarfRegAlias<!cast<Register>("V"#Index)> {
+ let SubRegIndices = [sub_vrm2, sub_vrm2_hi];
+ }
+ }
+
+ foreach Index = [0, 4, 8, 12, 16, 20, 24, 28] in {
+ def V#Index#M4 : RISCVRegWithSubRegs<Index, "v"#Index,
+ [!cast<Register>("V"#Index#"M2"),
+ !cast<Register>("V"#!add(Index, 2)#"M2")],
+ ["v"#Index]>,
+ DwarfRegAlias<!cast<Register>("V"#Index)> {
+ let SubRegIndices = [sub_vrm4, sub_vrm4_hi];
+ }
+ }
+
+ foreach Index = [0, 8, 16, 24] in {
+ def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index,
+ [!cast<Register>("V"#Index#"M4"),
+ !cast<Register>("V"#!add(Index, 4)#"M4")],
+ ["v"#Index]>,
+ DwarfRegAlias<!cast<Register>("V"#Index)> {
+ let SubRegIndices = [sub_vrm8, sub_vrm8_hi];
+ }
+ }
+
+ def VTYPE : RISCVReg<0, "vtype", ["vtype"]>;
+ def VL : RISCVReg<0, "vl", ["vl"]>;
+}
+
+class RegisterTypes<list<ValueType> reg_types> {
+ list<ValueType> types = reg_types;
+}
+
+// The order of registers represents the preferred allocation sequence,
+// meaning caller-save regs are listed before callee-save.
+def VR : RegisterClass<"RISCV", [nxv8i8, nxv4i16, nxv2i32, nxv1i64],
+ 64, (add
+ (sequence "V%u", 25, 31),
+ (sequence "V%u", 8, 24),
+ (sequence "V%u", 0, 7)
+ )> {
+ let Size = 64;
+}
+
+def VRM2 : RegisterClass<"RISCV", [nxv16i8, nxv8i16, nxv4i32, nxv2i64], 64,
+ (add V26M2, V28M2, V30M2, V8M2, V10M2, V12M2, V14M2, V16M2,
+ V18M2, V20M2, V22M2, V24M2, V0M2, V2M2, V4M2, V6M2)> {
+ let Size = 128;
+}
+
+def VRM4 : RegisterClass<"RISCV", [nxv32i8, nxv16i16, nxv8i32, nxv4i64], 64,
+ (add V28M4, V8M4, V12M4, V16M4, V20M4, V24M4, V0M4, V4M4)> {
+ let Size = 256;
+}
+
+def VRM8 : RegisterClass<"RISCV", [nxv32i16, nxv16i32, nxv8i64], 64,
+ (add V8M8, V16M8, V24M8, V0M8)> {
+ let Size = 512;
+}
+
+def VMaskVT : RegisterTypes<[nxv1i1, nxv2i1, nxv4i1, nxv8i1, nxv16i1, nxv32i1]>;
+
+def VM : RegisterClass<"RISCV", VMaskVT.types, 64, (add
+ (sequence "V%u", 25, 31),
+ (sequence "V%u", 8, 24),
+ (sequence "V%u", 0, 7))> {
+ let Size = 64;
+}
+
+def VMV0 : RegisterClass<"RISCV", VMaskVT.types, 64, (add V0)> {
+ let Size = 64;
+}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket32.td b/llvm/lib/Target/RISCV/RISCVSchedRocket32.td
index 487f72ebadc8..305e2b9b5927 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket32.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket32.td
@@ -17,6 +17,7 @@ def Rocket32Model : SchedMachineModel {
let LoadLatency = 3;
let MispredictPenalty = 3;
let CompleteModel = 1;
+ let UnsupportedFeatures = [HasStdExtV];
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVSchedRocket64.td b/llvm/lib/Target/RISCV/RISCVSchedRocket64.td
index da33443cc94a..e8514a275c45 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedRocket64.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedRocket64.td
@@ -16,6 +16,7 @@ def Rocket64Model : SchedMachineModel {
let IssueWidth = 1; // 1 micro-ops are dispatched per cycle.
let LoadLatency = 3;
let MispredictPenalty = 3;
+ let UnsupportedFeatures = [HasStdExtV];
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 8b339c3e4660..133542de2301 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -50,6 +50,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasStdExtZbs = false;
bool HasStdExtZbt = false;
bool HasStdExtZbproposedc = false;
+ bool HasStdExtV = false;
bool HasRV64 = false;
bool IsRV32E = false;
bool EnableLinkerRelax = false;
@@ -110,6 +111,7 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
bool hasStdExtZbs() const { return HasStdExtZbs; }
bool hasStdExtZbt() const { return HasStdExtZbt; }
bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
+ bool hasStdExtV() const { return HasStdExtV; }
bool is64Bit() const { return HasRV64; }
bool isRV32E() const { return IsRV32E; }
bool enableLinkerRelax() const { return EnableLinkerRelax; }
diff --git a/llvm/lib/Target/RISCV/RISCVSystemOperands.td b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
index 853dca0295c9..47a1240cfaaf 100644
--- a/llvm/lib/Target/RISCV/RISCVSystemOperands.td
+++ b/llvm/lib/Target/RISCV/RISCVSystemOperands.td
@@ -353,8 +353,19 @@ def : SysReg<"tdata3", 0x7A3>;
//===-----------------------------------------------
def : SysReg<"dcsr", 0x7B0>;
def : SysReg<"dpc", 0x7B1>;
+
// "dscratch" is an alternative name for "dscratch0" which appeared in earlier
// drafts of the RISC-V debug spec
let AltName = "dscratch" in
def : SysReg<"dscratch0", 0x7B2>;
def : SysReg<"dscratch1", 0x7B3>;
+
+//===-----------------------------------------------
+// User Vector CSRs
+//===-----------------------------------------------
+def : SysReg<"vstart", 0x008>;
+def : SysReg<"vxsat", 0x009>;
+def : SysReg<"vxrm", 0x00A>;
+def : SysReg<"vl", 0xC20>;
+def : SysReg<"vtype", 0xC21>;
+def : SysReg<"vlenb", 0xC22>;
diff --git a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
index 2aa1b23d24f0..4e6cdd8606b1 100644
--- a/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
+++ b/llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
@@ -45,7 +45,7 @@ enum {
InstFormatCJ = 16,
InstFormatOther = 17,
- InstFormatMask = 31
+ InstFormatMask = 31,
};
// RISC-V Specific Machine Operand Flags
diff --git a/llvm/test/MC/RISCV/rvv/add.s b/llvm/test/MC/RISCV/rvv/add.s
new file mode 100644
index 000000000000..f588d90a9c57
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/add.s
@@ -0,0 +1,339 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vadd.vv v8, v4, v20, v0.t
+# CHECK-INST: vadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 00 <unknown>
+
+vadd.vv v8, v4, v20
+# CHECK-INST: vadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 02 <unknown>
+
+vadd.vx v8, v4, a0, v0.t
+# CHECK-INST: vadd.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 00 <unknown>
+
+vadd.vx v8, v4, a0
+# CHECK-INST: vadd.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 02 <unknown>
+
+vadd.vi v8, v4, 15, v0.t
+# CHECK-INST: vadd.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 00 <unknown>
+
+vadd.vi v8, v4, 15
+# CHECK-INST: vadd.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 02 <unknown>
+
+vwaddu.vv v8, v4, v20, v0.t
+# CHECK-INST: vwaddu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a c0 <unknown>
+
+vwaddu.vv v8, v4, v20
+# CHECK-INST: vwaddu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a c2 <unknown>
+
+vwaddu.vx v8, v4, a0, v0.t
+# CHECK-INST: vwaddu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 c0 <unknown>
+
+vwaddu.vx v8, v4, a0
+# CHECK-INST: vwaddu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 c2 <unknown>
+
+vwadd.vv v8, v4, v20, v0.t
+# CHECK-INST: vwadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a c4 <unknown>
+
+vwadd.vv v8, v4, v20
+# CHECK-INST: vwadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a c6 <unknown>
+
+vwadd.vx v8, v4, a0, v0.t
+# CHECK-INST: vwadd.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 c4 <unknown>
+
+vwadd.vx v8, v4, a0
+# CHECK-INST: vwadd.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 c6 <unknown>
+
+vwaddu.wv v8, v4, v20, v0.t
+# CHECK-INST: vwaddu.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a d0 <unknown>
+
+vwaddu.wv v8, v4, v20
+# CHECK-INST: vwaddu.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a d2 <unknown>
+
+vwaddu.wx v8, v4, a0, v0.t
+# CHECK-INST: vwaddu.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 d0 <unknown>
+
+vwaddu.wx v8, v4, a0
+# CHECK-INST: vwaddu.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 d2 <unknown>
+
+vwadd.wv v8, v4, v20, v0.t
+# CHECK-INST: vwadd.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a d4 <unknown>
+
+vwadd.wv v8, v4, v20
+# CHECK-INST: vwadd.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a d6 <unknown>
+
+vwadd.wx v8, v4, a0, v0.t
+# CHECK-INST: vwadd.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 d4 <unknown>
+
+vwadd.wx v8, v4, a0
+# CHECK-INST: vwadd.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 d6 <unknown>
+
+vadc.vvm v8, v4, v20, v0
+# CHECK-INST: vadc.vvm v8, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 40 <unknown>
+
+vadc.vxm v8, v4, a0, v0
+# CHECK-INST: vadc.vxm v8, v4, a0, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 40 <unknown>
+
+vadc.vim v8, v4, 15, v0
+# CHECK-INST: vadc.vim v8, v4, 15, v0
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 40 <unknown>
+
+vmadc.vvm v8, v4, v20, v0
+# CHECK-INST: vmadc.vvm v8, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x44]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 44 <unknown>
+
+vmadc.vxm v8, v4, a0, v0
+# CHECK-INST: vmadc.vxm v8, v4, a0, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x44]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 44 <unknown>
+
+vmadc.vim v8, v4, 15, v0
+# CHECK-INST: vmadc.vim v8, v4, 15, v0
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x44]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 44 <unknown>
+
+vmadc.vv v8, v4, v20
+# CHECK-INST: vmadc.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x46]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 46 <unknown>
+
+vmadc.vx v8, v4, a0
+# CHECK-INST: vmadc.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x46]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 46 <unknown>
+
+vmadc.vi v8, v4, 15
+# CHECK-INST: vmadc.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x46]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 46 <unknown>
+
+vsaddu.vv v8, v4, v20, v0.t
+# CHECK-INST: vsaddu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 80 <unknown>
+
+vsaddu.vv v8, v4, v20
+# CHECK-INST: vsaddu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 82 <unknown>
+
+vsaddu.vx v8, v4, a0, v0.t
+# CHECK-INST: vsaddu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 80 <unknown>
+
+vsaddu.vx v8, v4, a0
+# CHECK-INST: vsaddu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 82 <unknown>
+
+vsaddu.vi v8, v4, 15, v0.t
+# CHECK-INST: vsaddu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 80 <unknown>
+
+vsaddu.vi v8, v4, 15
+# CHECK-INST: vsaddu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 82 <unknown>
+
+vsadd.vv v8, v4, v20, v0.t
+# CHECK-INST: vsadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x84]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 84 <unknown>
+
+vsadd.vv v8, v4, v20
+# CHECK-INST: vsadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x86]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 86 <unknown>
+
+vsadd.vx v8, v4, a0, v0.t
+# CHECK-INST: vsadd.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 84 <unknown>
+
+vsadd.vx v8, v4, a0
+# CHECK-INST: vsadd.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 86 <unknown>
+
+vsadd.vi v8, v4, 15, v0.t
+# CHECK-INST: vsadd.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x84]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 84 <unknown>
+
+vsadd.vi v8, v4, 15
+# CHECK-INST: vsadd.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x86]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 86 <unknown>
+
+vaadd.vv v8, v4, v20, v0.t
+# CHECK-INST: vaadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x24]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 24 <unknown>
+
+vaadd.vv v8, v4, v20
+# CHECK-INST: vaadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x26]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 26 <unknown>
+
+vaadd.vx v8, v4, a0, v0.t
+# CHECK-INST: vaadd.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 24 <unknown>
+
+vaadd.vx v8, v4, a0
+# CHECK-INST: vaadd.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 26 <unknown>
+
+vaaddu.vv v8, v4, v20, v0.t
+# CHECK-INST: vaaddu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 20 <unknown>
+
+vaaddu.vv v8, v4, v20
+# CHECK-INST: vaaddu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 22 <unknown>
+
+vaaddu.vx v8, v4, a0, v0.t
+# CHECK-INST: vaaddu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 20 <unknown>
+
+vaaddu.vx v8, v4, a0
+# CHECK-INST: vaaddu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 22 <unknown>
+
+vwcvt.x.x.v v8, v4, v0.t
+# CHECK-INST: vwcvt.x.x.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x40,0xc4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 40 c4 <unknown>
+
+vwcvt.x.x.v v8, v4
+# CHECK-INST: vwadd.vx v8, v4, zero
+# CHECK-ENCODING: [0x57,0x64,0x40,0xc6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 40 c6 <unknown>
+
+vwcvtu.x.x.v v8, v4, v0.t
+# CHECK-INST: vwcvtu.x.x.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x40,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 40 c0 <unknown>
+
+vwcvtu.x.x.v v8, v4
+# CHECK-INST: vwaddu.vx v8, v4, zero
+# CHECK-ENCODING: [0x57,0x64,0x40,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 40 c2 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/and.s b/llvm/test/MC/RISCV/rvv/and.s
new file mode 100644
index 000000000000..29021df3c292
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/and.s
@@ -0,0 +1,45 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vand.vv v8, v4, v20, v0.t
+# CHECK-INST: vand.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x24]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 24 <unknown>
+
+vand.vv v8, v4, v20
+# CHECK-INST: vand.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x26]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 26 <unknown>
+
+vand.vx v8, v4, a0, v0.t
+# CHECK-INST: vand.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 24 <unknown>
+
+vand.vx v8, v4, a0
+# CHECK-INST: vand.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 26 <unknown>
+
+vand.vi v8, v4, 15, v0.t
+# CHECK-INST: vand.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x24]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 24 <unknown>
+
+vand.vi v8, v4, 15
+# CHECK-INST: vand.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x26]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 26 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/clip.s b/llvm/test/MC/RISCV/rvv/clip.s
new file mode 100644
index 000000000000..c079409478d2
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/clip.s
@@ -0,0 +1,81 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vnclipu.wv v8, v4, v20, v0.t
+# CHECK-INST: vnclipu.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a b8 <unknown>
+
+vnclipu.wv v8, v4, v20
+# CHECK-INST: vnclipu.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a ba <unknown>
+
+vnclipu.wx v8, v4, a0, v0.t
+# CHECK-INST: vnclipu.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 b8 <unknown>
+
+vnclipu.wx v8, v4, a0
+# CHECK-INST: vnclipu.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 ba <unknown>
+
+vnclipu.wi v8, v4, 31, v0.t
+# CHECK-INST: vnclipu.wi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f b8 <unknown>
+
+vnclipu.wi v8, v4, 31
+# CHECK-INST: vnclipu.wi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f ba <unknown>
+
+vnclip.wv v8, v4, v20, v0.t
+# CHECK-INST: vnclip.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a bc <unknown>
+
+vnclip.wv v8, v4, v20
+# CHECK-INST: vnclip.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a be <unknown>
+
+vnclip.wx v8, v4, a0, v0.t
+# CHECK-INST: vnclip.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 bc <unknown>
+
+vnclip.wx v8, v4, a0
+# CHECK-INST: vnclip.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 be <unknown>
+
+vnclip.wi v8, v4, 31, v0.t
+# CHECK-INST: vnclip.wi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f bc <unknown>
+
+vnclip.wi v8, v4, 31
+# CHECK-INST: vnclip.wi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f be <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/compare.s b/llvm/test/MC/RISCV/rvv/compare.s
new file mode 100644
index 000000000000..7bf452f771a7
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/compare.s
@@ -0,0 +1,345 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vmseq.vv v8, v4, v20, v0.t
+# CHECK-INST: vmseq.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 60 <unknown>
+
+vmseq.vv v8, v4, v20
+# CHECK-INST: vmseq.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 62 <unknown>
+
+vmseq.vx v8, v4, a0, v0.t
+# CHECK-INST: vmseq.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 60 <unknown>
+
+vmseq.vx v8, v4, a0
+# CHECK-INST: vmseq.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 62 <unknown>
+
+vmseq.vi v8, v4, 15, v0.t
+# CHECK-INST: vmseq.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 60 <unknown>
+
+vmseq.vi v8, v4, 15
+# CHECK-INST: vmseq.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 62 <unknown>
+
+vmsne.vv v8, v4, v20, v0.t
+# CHECK-INST: vmsne.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x64]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 64 <unknown>
+
+vmsne.vv v8, v4, v20
+# CHECK-INST: vmsne.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 66 <unknown>
+
+vmsne.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsne.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 64 <unknown>
+
+vmsne.vx v8, v4, a0
+# CHECK-INST: vmsne.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 66 <unknown>
+
+vmsne.vi v8, v4, 15, v0.t
+# CHECK-INST: vmsne.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x64]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 64 <unknown>
+
+vmsne.vi v8, v4, 15
+# CHECK-INST: vmsne.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 66 <unknown>
+
+vmsltu.vv v8, v4, v20, v0.t
+# CHECK-INST: vmsltu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 68 <unknown>
+
+vmsltu.vv v8, v4, v20
+# CHECK-INST: vmsltu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 6a <unknown>
+
+vmsltu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsltu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 68 <unknown>
+
+vmsltu.vx v8, v4, a0
+# CHECK-INST: vmsltu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 6a <unknown>
+
+vmslt.vv v8, v4, v20, v0.t
+# CHECK-INST: vmslt.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 6c <unknown>
+
+vmslt.vv v8, v4, v20
+# CHECK-INST: vmslt.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 6e <unknown>
+
+vmslt.vx v8, v4, a0, v0.t
+# CHECK-INST: vmslt.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 6c <unknown>
+
+vmslt.vx v8, v4, a0
+# CHECK-INST: vmslt.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 6e <unknown>
+
+vmsleu.vv v8, v4, v20, v0.t
+# CHECK-INST: vmsleu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 70 <unknown>
+
+vmsleu.vv v8, v4, v20
+# CHECK-INST: vmsleu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 72 <unknown>
+
+vmsleu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsleu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 70 <unknown>
+
+vmsleu.vx v8, v4, a0
+# CHECK-INST: vmsleu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 72 <unknown>
+
+vmsleu.vi v8, v4, 15, v0.t
+# CHECK-INST: vmsleu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 70 <unknown>
+
+vmsleu.vi v8, v4, 15
+# CHECK-INST: vmsleu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 72 <unknown>
+
+vmsle.vv v8, v4, v20, v0.t
+# CHECK-INST: vmsle.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x74]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 74 <unknown>
+
+vmsle.vv v8, v4, v20
+# CHECK-INST: vmsle.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 76 <unknown>
+
+vmsle.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsle.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x74]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 74 <unknown>
+
+vmsle.vx v8, v4, a0
+# CHECK-INST: vmsle.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 76 <unknown>
+
+vmsle.vi v8, v4, 15, v0.t
+# CHECK-INST: vmsle.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x74]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 74 <unknown>
+
+vmsle.vi v8, v4, 15
+# CHECK-INST: vmsle.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 76 <unknown>
+
+vmsgtu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsgtu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 78 <unknown>
+
+vmsgtu.vx v8, v4, a0
+# CHECK-INST: vmsgtu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 7a <unknown>
+
+vmsgtu.vi v8, v4, 15, v0.t
+# CHECK-INST: vmsgtu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 78 <unknown>
+
+vmsgtu.vi v8, v4, 15
+# CHECK-INST: vmsgtu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 7a <unknown>
+
+vmsgt.vx v8, v4, a0, v0.t
+# CHECK-INST: vmsgt.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 7c <unknown>
+
+vmsgt.vx v8, v4, a0
+# CHECK-INST: vmsgt.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 7e <unknown>
+
+vmsgt.vi v8, v4, 15, v0.t
+# CHECK-INST: vmsgt.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 7c <unknown>
+
+vmsgt.vi v8, v4, 15
+# CHECK-INST: vmsgt.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 7e <unknown>
+
+vmsgtu.vv v8, v20, v4, v0.t
+# CHECK-INST: vmsltu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x68]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 68 <unknown>
+
+vmsgtu.vv v8, v20, v4
+# CHECK-INST: vmsltu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 6a <unknown>
+
+vmsgt.vv v8, v20, v4, v0.t
+# CHECK-INST: vmslt.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 6c <unknown>
+
+vmsgt.vv v8, v20, v4
+# CHECK-INST: vmslt.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 6e <unknown>
+
+vmsgeu.vv v8, v20, v4, v0.t
+# CHECK-INST: vmsleu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 70 <unknown>
+
+vmsgeu.vv v8, v20, v4
+# CHECK-INST: vmsleu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 72 <unknown>
+
+vmsge.vv v8, v20, v4, v0.t
+# CHECK-INST: vmsle.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x74]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 74 <unknown>
+
+vmsge.vv v8, v20, v4
+# CHECK-INST: vmsle.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 76 <unknown>
+
+vmsltu.vi v8, v4, 16, v0.t
+# CHECK-INST: vmsleu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 70 <unknown>
+
+vmsltu.vi v8, v4, 16
+# CHECK-INST: vmsleu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 72 <unknown>
+
+vmslt.vi v8, v4, 16, v0.t
+# CHECK-INST: vmsle.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x74]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 74 <unknown>
+
+vmslt.vi v8, v4, 16
+# CHECK-INST: vmsle.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 76 <unknown>
+
+vmsgeu.vi v8, v4, 16, v0.t
+# CHECK-INST: vmsgtu.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x78]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 78 <unknown>
+
+vmsgeu.vi v8, v4, 16
+# CHECK-INST: vmsgtu.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 7a <unknown>
+
+vmsge.vi v8, v4, 16, v0.t
+# CHECK-INST: vmsgt.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 7c <unknown>
+
+vmsge.vi v8, v4, 16
+# CHECK-INST: vmsgt.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 7e <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/convert.s b/llvm/test/MC/RISCV/rvv/convert.s
new file mode 100644
index 000000000000..e9f8860e97b5
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/convert.s
@@ -0,0 +1,189 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfcvt.xu.f.v v8, v4, v0.t
+# CHECK-INST: vfcvt.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x40,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 40 88 <unknown>
+
+vfcvt.xu.f.v v8, v4
+# CHECK-INST: vfcvt.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x40,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 40 8a <unknown>
+
+vfcvt.x.f.v v8, v4, v0.t
+# CHECK-INST: vfcvt.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x40,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 40 88 <unknown>
+
+vfcvt.x.f.v v8, v4
+# CHECK-INST: vfcvt.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x40,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 40 8a <unknown>
+
+vfcvt.f.xu.v v8, v4, v0.t
+# CHECK-INST: vfcvt.f.xu.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x41,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 41 88 <unknown>
+
+vfcvt.f.xu.v v8, v4
+# CHECK-INST: vfcvt.f.xu.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x41,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 41 8a <unknown>
+
+vfcvt.f.x.v v8, v4, v0.t
+# CHECK-INST: vfcvt.f.x.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x41,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 41 88 <unknown>
+
+vfcvt.f.x.v v8, v4
+# CHECK-INST: vfcvt.f.x.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x41,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 41 8a <unknown>
+
+vfwcvt.xu.f.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.xu.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x44,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 44 88 <unknown>
+
+vfwcvt.xu.f.v v8, v4
+# CHECK-INST: vfwcvt.xu.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x44,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 44 8a <unknown>
+
+vfwcvt.x.f.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.x.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x44,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 44 88 <unknown>
+
+vfwcvt.x.f.v v8, v4
+# CHECK-INST: vfwcvt.x.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x44,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 44 8a <unknown>
+
+vfwcvt.f.xu.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.f.xu.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x45,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 45 88 <unknown>
+
+vfwcvt.f.xu.v v8, v4
+# CHECK-INST: vfwcvt.f.xu.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x45,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 45 8a <unknown>
+
+vfwcvt.f.x.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.f.x.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x45,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 45 88 <unknown>
+
+vfwcvt.f.x.v v8, v4
+# CHECK-INST: vfwcvt.f.x.v v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x45,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 45 8a <unknown>
+
+vfwcvt.f.f.v v8, v4, v0.t
+# CHECK-INST: vfwcvt.f.f.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x46,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 46 88 <unknown>
+
+vfwcvt.f.f.v v8, v4
+# CHECK-INST: vfwcvt.f.f.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x46,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 46 8a <unknown>
+
+vfncvt.xu.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.xu.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x48,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 48 88 <unknown>
+
+vfncvt.xu.f.w v8, v4
+# CHECK-INST: vfncvt.xu.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x48,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 48 8a <unknown>
+
+vfncvt.x.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.x.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x48,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 48 88 <unknown>
+
+vfncvt.x.f.w v8, v4
+# CHECK-INST: vfncvt.x.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x48,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 48 8a <unknown>
+
+vfncvt.f.xu.w v8, v4, v0.t
+# CHECK-INST: vfncvt.f.xu.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x49,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 49 88 <unknown>
+
+vfncvt.f.xu.w v8, v4
+# CHECK-INST: vfncvt.f.xu.w v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x49,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 49 8a <unknown>
+
+vfncvt.f.x.w v8, v4, v0.t
+# CHECK-INST: vfncvt.f.x.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x49,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 49 88 <unknown>
+
+vfncvt.f.x.w v8, v4
+# CHECK-INST: vfncvt.f.x.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x49,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 49 8a <unknown>
+
+vfncvt.f.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.f.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 88 <unknown>
+
+vfncvt.f.f.w v8, v4
+# CHECK-INST: vfncvt.f.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 8a <unknown>
+
+vfncvt.rod.f.f.w v8, v4, v0.t
+# CHECK-INST: vfncvt.rod.f.f.w v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x94,0x4a,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 4a 88 <unknown>
+
+vfncvt.rod.f.f.w v8, v4
+# CHECK-INST: vfncvt.rod.f.f.w v8, v4
+# CHECK-ENCODING: [0x57,0x94,0x4a,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 94 4a 8a <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/div.s b/llvm/test/MC/RISCV/rvv/div.s
new file mode 100644
index 000000000000..e91e643fd8b5
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/div.s
@@ -0,0 +1,105 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vdivu.vv v8, v4, v20, v0.t
+# CHECK-INST: vdivu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 80 <unknown>
+
+vdivu.vv v8, v4, v20
+# CHECK-INST: vdivu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 82 <unknown>
+
+vdivu.vx v8, v4, a0, v0.t
+# CHECK-INST: vdivu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 80 <unknown>
+
+vdivu.vx v8, v4, a0
+# CHECK-INST: vdivu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 82 <unknown>
+
+vdiv.vv v8, v4, v20, v0.t
+# CHECK-INST: vdiv.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x84]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 84 <unknown>
+
+vdiv.vv v8, v4, v20
+# CHECK-INST: vdiv.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x86]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 86 <unknown>
+
+vdiv.vx v8, v4, a0, v0.t
+# CHECK-INST: vdiv.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 84 <unknown>
+
+vdiv.vx v8, v4, a0
+# CHECK-INST: vdiv.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 86 <unknown>
+
+vremu.vv v8, v4, v20, v0.t
+# CHECK-INST: vremu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 88 <unknown>
+
+vremu.vv v8, v4, v20
+# CHECK-INST: vremu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 8a <unknown>
+
+vremu.vx v8, v4, a0, v0.t
+# CHECK-INST: vremu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 88 <unknown>
+
+vremu.vx v8, v4, a0
+# CHECK-INST: vremu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 8a <unknown>
+
+vrem.vv v8, v4, v20, v0.t
+# CHECK-INST: vrem.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 8c <unknown>
+
+vrem.vv v8, v4, v20
+# CHECK-INST: vrem.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 8e <unknown>
+
+vrem.vx v8, v4, a0, v0.t
+# CHECK-INST: vrem.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 8c <unknown>
+
+vrem.vx v8, v4, a0
+# CHECK-INST: vrem.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 8e <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fadd.s b/llvm/test/MC/RISCV/rvv/fadd.s
new file mode 100644
index 000000000000..1c648c5a7634
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/fadd.s
@@ -0,0 +1,81 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfadd.vv v8, v4, v20, v0.t
+# CHECK-INST: vfadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 00 <unknown>
+
+vfadd.vv v8, v4, v20
+# CHECK-INST: vfadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 02 <unknown>
+
+vfadd.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfadd.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 00 <unknown>
+
+vfadd.vf v8, v4, fa0
+# CHECK-INST: vfadd.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 02 <unknown>
+
+vfwadd.vv v8, v4, v20, v0.t
+# CHECK-INST: vfwadd.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a c0 <unknown>
+
+vfwadd.vv v8, v4, v20
+# CHECK-INST: vfwadd.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a c2 <unknown>
+
+vfwadd.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfwadd.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 c0 <unknown>
+
+vfwadd.vf v8, v4, fa0
+# CHECK-INST: vfwadd.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 c2 <unknown>
+
+vfwadd.wv v8, v4, v20, v0.t
+# CHECK-INST: vfwadd.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a d0 <unknown>
+
+vfwadd.wv v8, v4, v20
+# CHECK-INST: vfwadd.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a d2 <unknown>
+
+vfwadd.wf v8, v4, fa0, v0.t
+# CHECK-INST: vfwadd.wf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xd0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 d0 <unknown>
+
+vfwadd.wf v8, v4, fa0
+# CHECK-INST: vfwadd.wf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xd2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 d2 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fcompare.s b/llvm/test/MC/RISCV/rvv/fcompare.s
new file mode 100644
index 000000000000..9ad55dc54a07
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/fcompare.s
@@ -0,0 +1,153 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vmfeq.vv v8, v4, v20, v0.t
+# CHECK-INST: vmfeq.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 60 <unknown>
+
+vmfeq.vv v8, v4, v20
+# CHECK-INST: vmfeq.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 62 <unknown>
+
+vmfeq.vf v8, v4, fa0, v0.t
+# CHECK-INST: vmfeq.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x60]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 60 <unknown>
+
+vmfeq.vf v8, v4, fa0
+# CHECK-INST: vmfeq.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 62 <unknown>
+
+vmfne.vv v8, v4, v20, v0.t
+# CHECK-INST: vmfne.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 70 <unknown>
+
+vmfne.vv v8, v4, v20
+# CHECK-INST: vmfne.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 72 <unknown>
+
+vmfne.vf v8, v4, fa0, v0.t
+# CHECK-INST: vmfne.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x70]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 70 <unknown>
+
+vmfne.vf v8, v4, fa0
+# CHECK-INST: vmfne.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 72 <unknown>
+
+vmflt.vv v8, v4, v20, v0.t
+# CHECK-INST: vmflt.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 6c <unknown>
+
+vmflt.vv v8, v4, v20
+# CHECK-INST: vmflt.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 6e <unknown>
+
+vmflt.vf v8, v4, fa0, v0.t
+# CHECK-INST: vmflt.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 6c <unknown>
+
+vmflt.vf v8, v4, fa0
+# CHECK-INST: vmflt.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 6e <unknown>
+
+vmfle.vv v8, v4, v20, v0.t
+# CHECK-INST: vmfle.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x64]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 64 <unknown>
+
+vmfle.vv v8, v4, v20
+# CHECK-INST: vmfle.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 66 <unknown>
+
+vmfle.vf v8, v4, fa0, v0.t
+# CHECK-INST: vmfle.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x64]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 64 <unknown>
+
+vmfle.vf v8, v4, fa0
+# CHECK-INST: vmfle.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 66 <unknown>
+
+vmfgt.vf v8, v4, fa0, v0.t
+# CHECK-INST: vmfgt.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x74]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 74 <unknown>
+
+vmfgt.vf v8, v4, fa0
+# CHECK-INST: vmfgt.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 76 <unknown>
+
+vmfge.vf v8, v4, fa0, v0.t
+# CHECK-INST: vmfge.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x7c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 7c <unknown>
+
+vmfge.vf v8, v4, fa0
+# CHECK-INST: vmfge.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 7e <unknown>
+
+vmfgt.vv v8, v20, v4, v0.t
+# CHECK-INST: vmflt.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x6c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 6c <unknown>
+
+vmfgt.vv v8, v20, v4
+# CHECK-INST: vmflt.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 6e <unknown>
+
+vmfge.vv v8, v20, v4, v0.t
+# CHECK-INST: vmfle.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x64]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 64 <unknown>
+
+vmfge.vv v8, v20, v4
+# CHECK-INST: vmfle.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 66 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fdiv.s b/llvm/test/MC/RISCV/rvv/fdiv.s
new file mode 100644
index 000000000000..28c067ec4fcd
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/fdiv.s
@@ -0,0 +1,45 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfdiv.vv v8, v4, v20, v0.t
+# CHECK-INST: vfdiv.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 80 <unknown>
+
+vfdiv.vv v8, v4, v20
+# CHECK-INST: vfdiv.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 82 <unknown>
+
+vfdiv.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfdiv.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 80 <unknown>
+
+vfdiv.vf v8, v4, fa0
+# CHECK-INST: vfdiv.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x82]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 82 <unknown>
+
+vfrdiv.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfrdiv.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x84]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 84 <unknown>
+
+vfrdiv.vf v8, v4, fa0
+# CHECK-INST: vfrdiv.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x86]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 86 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fmacc.s b/llvm/test/MC/RISCV/rvv/fmacc.s
new file mode 100644
index 000000000000..4dc39e4d57b3
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/fmacc.s
@@ -0,0 +1,297 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: vfmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a b0 <unknown>
+
+vfmacc.vv v8, v20, v4
+# CHECK-INST: vfmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a b2 <unknown>
+
+vfmacc.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfmacc.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 b0 <unknown>
+
+vfmacc.vf v8, fa0, v4
+# CHECK-INST: vfmacc.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 b2 <unknown>
+
+vfnmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: vfnmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a b4 <unknown>
+
+vfnmacc.vv v8, v20, v4
+# CHECK-INST: vfnmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a b6 <unknown>
+
+vfnmacc.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfnmacc.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 b4 <unknown>
+
+vfnmacc.vf v8, fa0, v4
+# CHECK-INST: vfnmacc.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 b6 <unknown>
+
+vfmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: vfmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a b8 <unknown>
+
+vfmsac.vv v8, v20, v4
+# CHECK-INST: vfmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a ba <unknown>
+
+vfmsac.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfmsac.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xb8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 b8 <unknown>
+
+vfmsac.vf v8, fa0, v4
+# CHECK-INST: vfmsac.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xba]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 ba <unknown>
+
+vfnmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: vfnmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a bc <unknown>
+
+vfnmsac.vv v8, v20, v4
+# CHECK-INST: vfnmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a be <unknown>
+
+vfnmsac.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfnmsac.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 bc <unknown>
+
+vfnmsac.vf v8, fa0, v4
+# CHECK-INST: vfnmsac.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 be <unknown>
+
+vfmadd.vv v8, v20, v4, v0.t
+# CHECK-INST: vfmadd.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a a0 <unknown>
+
+vfmadd.vv v8, v20, v4
+# CHECK-INST: vfmadd.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a a2 <unknown>
+
+vfmadd.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfmadd.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 a0 <unknown>
+
+vfmadd.vf v8, fa0, v4
+# CHECK-INST: vfmadd.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 a2 <unknown>
+
+vfnmadd.vv v8, v20, v4, v0.t
+# CHECK-INST: vfnmadd.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a a4 <unknown>
+
+vfnmadd.vv v8, v20, v4
+# CHECK-INST: vfnmadd.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a a6 <unknown>
+
+vfnmadd.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfnmadd.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 a4 <unknown>
+
+vfnmadd.vf v8, fa0, v4
+# CHECK-INST: vfnmadd.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 a6 <unknown>
+
+vfmsub.vv v8, v20, v4, v0.t
+# CHECK-INST: vfmsub.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a a8 <unknown>
+
+vfmsub.vv v8, v20, v4
+# CHECK-INST: vfmsub.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a aa <unknown>
+
+vfmsub.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfmsub.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 a8 <unknown>
+
+vfmsub.vf v8, fa0, v4
+# CHECK-INST: vfmsub.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 aa <unknown>
+
+vfnmsub.vv v8, v20, v4, v0.t
+# CHECK-INST: vfnmsub.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a ac <unknown>
+
+vfnmsub.vv v8, v20, v4
+# CHECK-INST: vfnmsub.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a ae <unknown>
+
+vfnmsub.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfnmsub.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 ac <unknown>
+
+vfnmsub.vf v8, fa0, v4
+# CHECK-INST: vfnmsub.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 ae <unknown>
+
+vfwmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: vfwmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a f0 <unknown>
+
+vfwmacc.vv v8, v20, v4
+# CHECK-INST: vfwmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a f2 <unknown>
+
+vfwmacc.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfwmacc.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 f0 <unknown>
+
+vfwmacc.vf v8, fa0, v4
+# CHECK-INST: vfwmacc.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 f2 <unknown>
+
+vfwnmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: vfwnmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a f4 <unknown>
+
+vfwnmacc.vv v8, v20, v4
+# CHECK-INST: vfwnmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a f6 <unknown>
+
+vfwnmacc.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfwnmacc.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 f4 <unknown>
+
+vfwnmacc.vf v8, fa0, v4
+# CHECK-INST: vfwnmacc.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 f6 <unknown>
+
+vfwmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: vfwmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a f8 <unknown>
+
+vfwmsac.vv v8, v20, v4
+# CHECK-INST: vfwmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a fa <unknown>
+
+vfwmsac.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfwmsac.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 f8 <unknown>
+
+vfwmsac.vf v8, fa0, v4
+# CHECK-INST: vfwmsac.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 fa <unknown>
+
+vfwnmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: vfwnmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a fc <unknown>
+
+vfwnmsac.vv v8, v20, v4
+# CHECK-INST: vfwnmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a fe <unknown>
+
+vfwnmsac.vf v8, fa0, v4, v0.t
+# CHECK-INST: vfwnmsac.vf v8, fa0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 fc <unknown>
+
+vfwnmsac.vf v8, fa0, v4
+# CHECK-INST: vfwnmsac.vf v8, fa0, v4
+# CHECK-ENCODING: [0x57,0x54,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 fe <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fminmax.s b/llvm/test/MC/RISCV/rvv/fminmax.s
new file mode 100644
index 000000000000..8ce3db16b3ea
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/fminmax.s
@@ -0,0 +1,57 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfmin.vv v8, v4, v20, v0.t
+# CHECK-INST: vfmin.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 10 <unknown>
+
+vfmin.vv v8, v4, v20
+# CHECK-INST: vfmin.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 12 <unknown>
+
+vfmin.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfmin.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 10 <unknown>
+
+vfmin.vf v8, v4, fa0
+# CHECK-INST: vfmin.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 12 <unknown>
+
+vfmax.vv v8, v4, v20, v0.t
+# CHECK-INST: vfmax.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 18 <unknown>
+
+vfmax.vv v8, v4, v20
+# CHECK-INST: vfmax.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 1a <unknown>
+
+vfmax.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfmax.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 18 <unknown>
+
+vfmax.vf v8, v4, fa0
+# CHECK-INST: vfmax.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 1a <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fmul.s b/llvm/test/MC/RISCV/rvv/fmul.s
new file mode 100644
index 000000000000..82f3bd3a4bf6
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/fmul.s
@@ -0,0 +1,57 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfmul.vv v8, v4, v20, v0.t
+# CHECK-INST: vfmul.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 90 <unknown>
+
+vfmul.vv v8, v4, v20
+# CHECK-INST: vfmul.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 92 <unknown>
+
+vfmul.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfmul.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 90 <unknown>
+
+vfmul.vf v8, v4, fa0
+# CHECK-INST: vfmul.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 92 <unknown>
+
+vfwmul.vv v8, v4, v20, v0.t
+# CHECK-INST: vfwmul.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a e0 <unknown>
+
+vfwmul.vv v8, v4, v20
+# CHECK-INST: vfwmul.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a e2 <unknown>
+
+vfwmul.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfwmul.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 e0 <unknown>
+
+vfwmul.vf v8, v4, fa0
+# CHECK-INST: vfwmul.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 e2 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fmv.s b/llvm/test/MC/RISCV/rvv/fmv.s
new file mode 100644
index 000000000000..74e3f0268bda
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/fmv.s
@@ -0,0 +1,27 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfmv.v.f v8, fa0
+# CHECK-INST: vfmv.v.f v8, fa0
+# CHECK-ENCODING: [0x57,0x54,0x05,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 05 5e <unknown>
+
+vfmv.f.s fa0, v4
+# CHECK-INST: vfmv.f.s fa0, v4
+# CHECK-ENCODING: [0x57,0x15,0x40,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 15 40 42 <unknown>
+
+vfmv.s.f v8, fa0
+# CHECK-INST: vfmv.s.f v8, fa0
+# CHECK-ENCODING: [0x57,0x54,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 05 42 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fothers.s b/llvm/test/MC/RISCV/rvv/fothers.s
new file mode 100644
index 000000000000..768800def424
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/fothers.s
@@ -0,0 +1,39 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfsqrt.v v8, v4, v0.t
+# CHECK-INST: vfsqrt.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x40,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 40 8c <unknown>
+
+vfsqrt.v v8, v4
+# CHECK-INST: vfsqrt.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x40,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 40 8e <unknown>
+
+vfclass.v v8, v4, v0.t
+# CHECK-INST: vfclass.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x48,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 48 8c <unknown>
+
+vfclass.v v8, v4
+# CHECK-INST: vfclass.v v8, v4
+# CHECK-ENCODING: [0x57,0x14,0x48,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 48 8e <unknown>
+
+vfmerge.vfm v8, v4, fa0, v0
+# CHECK-INST: vfmerge.vfm v8, v4, fa0, v0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 5c <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/freduction.s b/llvm/test/MC/RISCV/rvv/freduction.s
new file mode 100644
index 000000000000..2131dadff8ca
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/freduction.s
@@ -0,0 +1,81 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfredosum.vs v8, v4, v20, v0.t
+# CHECK-INST: vfredosum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 0c <unknown>
+
+vfredosum.vs v8, v4, v20
+# CHECK-INST: vfredosum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 0e <unknown>
+
+vfredsum.vs v8, v4, v20, v0.t
+# CHECK-INST: vfredsum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 04 <unknown>
+
+vfredsum.vs v8, v4, v20
+# CHECK-INST: vfredsum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 06 <unknown>
+
+vfredmax.vs v8, v4, v20, v0.t
+# CHECK-INST: vfredmax.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 1c <unknown>
+
+vfredmax.vs v8, v4, v20
+# CHECK-INST: vfredmax.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 1e <unknown>
+
+vfredmin.vs v8, v4, v20, v0.t
+# CHECK-INST: vfredmin.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x14]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 14 <unknown>
+
+vfredmin.vs v8, v4, v20
+# CHECK-INST: vfredmin.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x16]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 16 <unknown>
+
+vfwredosum.vs v8, v4, v20, v0.t
+# CHECK-INST: vfwredosum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xcc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a cc <unknown>
+
+vfwredosum.vs v8, v4, v20
+# CHECK-INST: vfwredosum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xce]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a ce <unknown>
+
+vfwredsum.vs v8, v4, v20, v0.t
+# CHECK-INST: vfwredsum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a c4 <unknown>
+
+vfwredsum.vs v8, v4, v20
+# CHECK-INST: vfwredsum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a c6 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/fsub.s b/llvm/test/MC/RISCV/rvv/fsub.s
new file mode 100644
index 000000000000..753da9a202b1
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/fsub.s
@@ -0,0 +1,93 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfsub.vv v8, v4, v20, v0.t
+# CHECK-INST: vfsub.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 08 <unknown>
+
+vfsub.vv v8, v4, v20
+# CHECK-INST: vfsub.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 0a <unknown>
+
+vfsub.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfsub.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 08 <unknown>
+
+vfsub.vf v8, v4, fa0
+# CHECK-INST: vfsub.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 0a <unknown>
+
+vfrsub.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfrsub.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 9c <unknown>
+
+vfrsub.vf v8, v4, fa0
+# CHECK-INST: vfrsub.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 9e <unknown>
+
+vfwsub.vv v8, v4, v20, v0.t
+# CHECK-INST: vfwsub.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xc8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a c8 <unknown>
+
+vfwsub.vv v8, v4, v20
+# CHECK-INST: vfwsub.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xca]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a ca <unknown>
+
+vfwsub.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfwsub.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xc8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 c8 <unknown>
+
+vfwsub.vf v8, v4, fa0
+# CHECK-INST: vfwsub.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xca]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 ca <unknown>
+
+vfwsub.wv v8, v4, v20, v0.t
+# CHECK-INST: vfwsub.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xd8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a d8 <unknown>
+
+vfwsub.wv v8, v4, v20
+# CHECK-INST: vfwsub.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0xda]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a da <unknown>
+
+vfwsub.wf v8, v4, fa0, v0.t
+# CHECK-INST: vfwsub.wf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0xd8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 d8 <unknown>
+
+vfwsub.wf v8, v4, fa0
+# CHECK-INST: vfwsub.wf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0xda]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 da <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s
new file mode 100644
index 000000000000..814093eba505
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/invalid.s
@@ -0,0 +1,780 @@
+# RUN: not llvm-mc -triple=riscv64 --mattr=+experimental-v --mattr=+f %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+
+vsetvli a2, a0, e31
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+
+vsetvli a2, a0, e32,m3
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+
+vsetvli a2, a0, m1,e32
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+
+vsetvli a2, a0, e32,m16
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+
+vsetvli a2, a0, e2048,m8
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+
+vsetvli a2, a0, e1,m8
+# CHECK-ERROR: operand must be e[8|16|32|64|128|256|512|1024],m[1|2|4|8]
+
+vadd.vv v1, v3, v2, v4.t
+# CHECK-ERROR: operand must be v0.t
+
+vadd.vv v1, v3, v2, v0
+# CHECK-ERROR: expected '.t' suffix
+
+vmslt.vi v1, v2, -16
+# CHECK-ERROR: immediate must be in the range [-15, 16]
+
+vmslt.vi v1, v2, 17
+# CHECK-ERROR: immediate must be in the range [-15, 16]
+
+viota.m v0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: viota.m v0, v2, v0.t
+
+viota.m v2, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: viota.m v2, v2
+
+vfwcvt.xu.f.v v0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwcvt.xu.f.v v0, v2, v0.t
+
+vfwcvt.xu.f.v v2, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwcvt.xu.f.v v2, v2
+
+vfwcvt.xu.f.v v2, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwcvt.xu.f.v v2, v3
+
+vfwcvt.x.f.v v0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwcvt.x.f.v v0, v2, v0.t
+
+vfwcvt.x.f.v v2, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwcvt.x.f.v v2, v2
+
+vfwcvt.x.f.v v2, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwcvt.x.f.v v2, v3
+
+vfwcvt.f.xu.v v0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v0, v2, v0.t
+
+vfwcvt.f.xu.v v2, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v2, v2
+
+vfwcvt.f.xu.v v2, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwcvt.f.xu.v v2, v3
+
+vfwcvt.f.x.v v0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwcvt.f.x.v v0, v2, v0.t
+
+vfwcvt.f.x.v v2, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwcvt.f.x.v v2, v2
+
+vfwcvt.f.x.v v2, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwcvt.f.x.v v2, v3
+
+vfwcvt.f.f.v v0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwcvt.f.f.v v0, v2, v0.t
+
+vfwcvt.f.f.v v2, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwcvt.f.f.v v2, v2
+
+vfwcvt.f.f.v v2, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwcvt.f.f.v v2, v3
+
+vslideup.vx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vslideup.vx v0, v2, a0, v0.t
+
+vslideup.vx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vslideup.vx v2, v2, a0
+
+vslideup.vi v0, v2, 31, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vslideup.vi v0, v2, 31, v0.t
+
+vslideup.vi v2, v2, 31
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vslideup.vi v2, v2, 31
+
+vslide1up.vx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vslide1up.vx v0, v2, a0, v0.t
+
+vslide1up.vx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vslide1up.vx v2, v2, a0
+
+vnsrl.wv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnsrl.wv v2, v2, v4
+
+vnsrl.wv v3, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnsrl.wv v3, v2, v4
+
+vnsrl.wx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnsrl.wx v2, v2, a0
+
+vnsrl.wi v2, v2, 31
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnsrl.wi v2, v2, 31
+
+vnsra.wv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnsra.wv v2, v2, v4
+
+vnsra.wv v3, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnsra.wv v3, v2, v4
+
+vnsra.wx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnsra.wx v2, v2, a0
+
+vnsra.wi v2, v2, 31
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnsra.wi v2, v2, 31
+
+vnclipu.wv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnclipu.wv v2, v2, v4
+
+vnclipu.wv v3, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnclipu.wv v3, v2, v4
+
+vnclipu.wx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnclipu.wx v2, v2, a0
+
+vnclipu.wi v2, v2, 31
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnclipu.wi v2, v2, 31
+
+vnclip.wv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnclip.wv v2, v2, v4
+
+vnclip.wv v3, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnclip.wv v3, v2, v4
+
+vnclip.wx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnclip.wx v2, v2, a0
+
+vnclip.wi v2, v2, 31
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vnclip.wi v2, v2, 31
+
+vfncvt.xu.f.w v2, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfncvt.xu.f.w v2, v2
+
+vfncvt.xu.f.w v3, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfncvt.xu.f.w v3, v2
+
+vfncvt.x.f.w v2, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfncvt.x.f.w v2, v2
+
+vfncvt.x.f.w v3, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfncvt.x.f.w v3, v2
+
+vfncvt.f.xu.w v2, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfncvt.f.xu.w v2, v2
+
+vfncvt.f.xu.w v3, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfncvt.f.xu.w v3, v2
+
+vfncvt.f.x.w v2, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfncvt.f.x.w v2, v2
+
+vfncvt.f.x.w v3, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfncvt.f.x.w v3, v2
+
+vfncvt.f.f.w v2, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfncvt.f.f.w v2, v2
+
+vfncvt.f.f.w v3, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfncvt.f.f.w v3, v2
+
+vfncvt.rod.f.f.w v2, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfncvt.rod.f.f.w v2, v2
+
+vfncvt.rod.f.f.w v3, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfncvt.rod.f.f.w v3, v2
+
+vrgather.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vrgather.vv v0, v2, v4, v0.t
+
+vrgather.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vrgather.vv v2, v2, v4
+
+vrgather.vx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vrgather.vx v0, v2, a0, v0.t
+
+vrgather.vx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vrgather.vx v2, v2, a0
+
+vrgather.vi v0, v2, 31, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vrgather.vi v0, v2, 31, v0.t
+
+vrgather.vi v2, v2, 31
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vrgather.vi v2, v2, 31
+
+vwaddu.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwaddu.vv v0, v2, v4, v0.t
+
+vwaddu.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwaddu.vv v2, v2, v4
+
+vwaddu.vv v2, v3, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwaddu.vv v2, v3, v4
+
+vwsubu.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwsubu.vv v0, v2, v4, v0.t
+
+vwsubu.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsubu.vv v2, v2, v4
+
+vwsubu.vv v2, v3, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsubu.vv v2, v3, v4
+
+vwadd.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwadd.vv v0, v2, v4, v0.t
+
+vwadd.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwadd.vv v2, v2, v4
+
+vwadd.vv v2, v3, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwadd.vv v2, v3, v4
+
+vwsub.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwsub.vv v0, v2, v4, v0.t
+
+vwsub.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsub.vv v2, v2, v4
+
+vwsub.vv v2, v3, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsub.vv v2, v3, v4
+
+vwmul.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmul.vv v0, v2, v4, v0.t
+
+vwmul.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmul.vv v2, v2, v4
+
+vwmul.vv v2, v3, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmul.vv v2, v3, v4
+
+vwmulu.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmulu.vv v0, v2, v4, v0.t
+
+vwmulu.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmulu.vv v2, v2, v4
+
+vwmulu.vv v2, v3, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmulu.vv v2, v3, v4
+
+vwmulsu.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmulsu.vv v0, v2, v4, v0.t
+
+vwmulsu.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmulsu.vv v2, v2, v4
+
+vwmulsu.vv v2, v3, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmulsu.vv v2, v3, v4
+
+vwmaccu.vv v0, v4, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmaccu.vv v0, v4, v2, v0.t
+
+vwmaccu.vv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmaccu.vv v2, v4, v2
+
+vwmaccu.vv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmaccu.vv v2, v4, v3
+
+vwmacc.vv v0, v4, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmacc.vv v0, v4, v2, v0.t
+
+vwmacc.vv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmacc.vv v2, v4, v2
+
+vwmacc.vv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmacc.vv v2, v4, v3
+
+vwmaccsu.vv v0, v4, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmaccsu.vv v0, v4, v2, v0.t
+
+vwmaccsu.vv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmaccsu.vv v2, v4, v2
+
+vwmaccsu.vv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmaccsu.vv v2, v4, v3
+
+vfwadd.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwadd.vv v0, v2, v4, v0.t
+
+vfwadd.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwadd.vv v2, v2, v4
+
+vfwadd.vv v2, v3, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwadd.vv v2, v3, v4
+
+vfwsub.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwsub.vv v0, v2, v4, v0.t
+
+vfwsub.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwsub.vv v2, v2, v4
+
+vfwsub.vv v2, v3, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwsub.vv v2, v3, v4
+
+vfwmul.vv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwmul.vv v0, v2, v4, v0.t
+
+vfwmul.vv v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwmul.vv v2, v2, v4
+
+vfwmul.vv v2, v3, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwmul.vv v2, v3, v4
+
+vfwmacc.vv v0, v4, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwmacc.vv v0, v4, v2, v0.t
+
+vfwmacc.vv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwmacc.vv v2, v4, v2
+
+vfwmacc.vv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwmacc.vv v2, v4, v3
+
+vfwnmacc.vv v0, v4, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwnmacc.vv v0, v4, v2, v0.t
+
+vfwnmacc.vv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwnmacc.vv v2, v4, v2
+
+vfwnmacc.vv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwnmacc.vv v2, v4, v3
+
+vfwmsac.vv v0, v4, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwmsac.vv v0, v4, v2, v0.t
+
+vfwmsac.vv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwmsac.vv v2, v4, v2
+
+vfwmsac.vv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwmsac.vv v2, v4, v3
+
+vfwnmsac.vv v0, v4, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwnmsac.vv v0, v4, v2, v0.t
+
+vfwnmsac.vv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwnmsac.vv v2, v4, v2
+
+vfwnmsac.vv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwnmsac.vv v2, v4, v3
+
+vwaddu.vx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwaddu.vx v0, v2, a0, v0.t
+
+vwaddu.vx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwaddu.vx v2, v2, a0
+
+vwaddu.vx v2, v3, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwaddu.vx v2, v3, a0
+
+vwsubu.vx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwsubu.vx v0, v2, a0, v0.t
+
+vwsubu.vx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsubu.vx v2, v2, a0
+
+vwsubu.vx v2, v3, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsubu.vx v2, v3, a0
+
+vwadd.vx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwadd.vx v0, v2, a0, v0.t
+
+vwadd.vx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwadd.vx v2, v2, a0
+
+vwadd.vx v2, v3, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwadd.vx v2, v3, a0
+
+vwsub.vx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwsub.vx v0, v2, a0, v0.t
+
+vwsub.vx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsub.vx v2, v2, a0
+
+vwsub.vx v2, v3, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsub.vx v2, v3, a0
+
+vwmul.vx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmul.vx v0, v2, a0, v0.t
+
+vwmul.vx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmul.vx v2, v2, a0
+
+vwmul.vx v2, v3, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmul.vx v2, v3, a0
+
+vwmulu.vx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmulu.vx v0, v2, a0, v0.t
+
+vwmulu.vx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmulu.vx v2, v2, a0
+
+vwmulu.vx v2, v3, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmulu.vx v2, v3, a0
+
+vwmulsu.vx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmulsu.vx v0, v2, a0, v0.t
+
+vwmulsu.vx v2, v2, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmulsu.vx v2, v2, a0
+
+vwmulsu.vx v2, v3, a0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmulsu.vx v2, v3, a0
+
+vwmaccu.vx v0, a0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmaccu.vx v0, a0, v2, v0.t
+
+vwmaccu.vx v2, a0, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmaccu.vx v2, a0, v2
+
+vwmaccu.vx v2, a0, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmaccu.vx v2, a0, v3
+
+vwmacc.vx v0, a0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmacc.vx v0, a0, v2, v0.t
+
+vwmacc.vx v2, a0, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmacc.vx v2, a0, v2
+
+vwmacc.vx v2, a0, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmacc.vx v2, a0, v3
+
+vwmaccsu.vx v0, a0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmaccsu.vx v0, a0, v2, v0.t
+
+vwmaccsu.vx v2, a0, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmaccsu.vx v2, a0, v2
+
+vwmaccsu.vx v2, a0, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmaccsu.vx v2, a0, v3
+
+vwmaccus.vx v0, a0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwmaccus.vx v0, a0, v2, v0.t
+
+vwmaccus.vx v2, a0, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmaccus.vx v2, a0, v2
+
+vwmaccus.vx v2, a0, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwmaccus.vx v2, a0, v3
+
+vfwadd.vf v0, v2, fa0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwadd.vf v0, v2, fa0, v0.t
+
+vfwadd.vf v2, v2, fa0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwadd.vf v2, v2, fa0
+
+vfwadd.vf v2, v3, fa0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwadd.vf v2, v3, fa0
+
+vfwsub.vf v0, v2, fa0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwsub.vf v0, v2, fa0, v0.t
+
+vfwsub.vf v2, v2, fa0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwsub.vf v2, v2, fa0
+
+vfwsub.vf v2, v3, fa0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwsub.vf v2, v3, fa0
+
+vfwmul.vf v0, v2, fa0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwmul.vf v0, v2, fa0, v0.t
+
+vfwmul.vf v2, v2, fa0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwmul.vf v2, v2, fa0
+
+vfwmul.vf v2, v3, fa0
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwmul.vf v2, v3, fa0
+
+vfwmacc.vf v0, fa0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwmacc.vf v0, fa0, v2, v0.t
+
+vfwmacc.vf v2, fa0, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwmacc.vf v2, fa0, v2
+
+vfwmacc.vf v2, fa0, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwmacc.vf v2, fa0, v3
+
+vfwnmacc.vf v0, fa0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwnmacc.vf v0, fa0, v2, v0.t
+
+vfwnmacc.vf v2, fa0, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwnmacc.vf v2, fa0, v2
+
+vfwnmacc.vf v2, fa0, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwnmacc.vf v2, fa0, v3
+
+vfwmsac.vf v0, fa0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwmsac.vf v0, fa0, v2, v0.t
+
+vfwmsac.vf v2, fa0, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwmsac.vf v2, fa0, v2
+
+vfwmsac.vf v2, fa0, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwmsac.vf v2, fa0, v3
+
+vfwnmsac.vf v0, fa0, v2, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwnmsac.vf v0, fa0, v2, v0.t
+
+vfwnmsac.vf v2, fa0, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwnmsac.vf v2, fa0, v2
+
+vfwnmsac.vf v2, fa0, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwnmsac.vf v2, fa0, v3
+
+vcompress.vm v2, v2, v4
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vcompress.vm v2, v2, v4
+
+vwaddu.wv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwaddu.wv v0, v2, v4, v0.t
+
+vwaddu.wv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwaddu.wv v2, v4, v2
+
+vwaddu.wv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwaddu.wv v2, v4, v3
+
+vwsubu.wv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwsubu.wv v0, v2, v4, v0.t
+
+vwsubu.wv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsubu.wv v2, v4, v2
+
+vwsubu.wv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsubu.wv v2, v4, v3
+
+vwadd.wv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwadd.wv v0, v2, v4, v0.t
+
+vwadd.wv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwadd.wv v2, v4, v2
+
+vwadd.wv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwadd.wv v2, v4, v3
+
+vwsub.wv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwsub.wv v0, v2, v4, v0.t
+
+vwsub.wv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsub.wv v2, v4, v2
+
+vwsub.wv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vwsub.wv v2, v4, v3
+
+vfwadd.wv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwadd.wv v0, v2, v4, v0.t
+
+vfwadd.wv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwadd.wv v2, v4, v2
+
+vfwadd.wv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwadd.wv v2, v4, v3
+
+vfwsub.wv v0, v2, v4, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwsub.wv v0, v2, v4, v0.t
+
+vfwsub.wv v2, v4, v2
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwsub.wv v2, v4, v2
+
+vfwsub.wv v2, v4, v3
+# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
+# CHECK-ERROR-LABEL: vfwsub.wv v2, v4, v3
+
+vwaddu.wx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwaddu.wx v0, v2, a0, v0.t
+
+vwsubu.wx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwsubu.wx v0, v2, a0, v0.t
+
+vwadd.wx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwadd.wx v0, v2, a0, v0.t
+
+vwsub.wx v0, v2, a0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vwsub.wx v0, v2, a0, v0.t
+
+vfwadd.wf v0, v2, fa0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwadd.wf v0, v2, fa0, v0.t
+
+vfwsub.wf v0, v2, fa0, v0.t
+# CHECK-ERROR: The destination vector register group cannot overlap the mask register.
+# CHECK-ERROR-LABEL: vfwsub.wf v0, v2, fa0, v0.t
diff --git a/llvm/test/MC/RISCV/rvv/load.s b/llvm/test/MC/RISCV/rvv/load.s
new file mode 100644
index 000000000000..c8284b561f4a
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/load.s
@@ -0,0 +1,339 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vlb.v v8, (a0), v0.t
+# CHECK-INST: vlb.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 05 10 <unknown>
+
+vlb.v v8, (a0)
+# CHECK-INST: vlb.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 05 12 <unknown>
+
+vlh.v v8, (a0), v0.t
+# CHECK-INST: vlh.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 05 10 <unknown>
+
+vlh.v v8, (a0)
+# CHECK-INST: vlh.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 05 12 <unknown>
+
+vlw.v v8, (a0), v0.t
+# CHECK-INST: vlw.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 10 <unknown>
+
+vlw.v v8, (a0)
+# CHECK-INST: vlw.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 12 <unknown>
+
+vlbu.v v8, (a0), v0.t
+# CHECK-INST: vlbu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 05 00 <unknown>
+
+vlbu.v v8, (a0)
+# CHECK-INST: vlbu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 05 02 <unknown>
+
+vlhu.v v8, (a0), v0.t
+# CHECK-INST: vlhu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 05 00 <unknown>
+
+vlhu.v v8, (a0)
+# CHECK-INST: vlhu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 05 02 <unknown>
+
+vlwu.v v8, (a0), v0.t
+# CHECK-INST: vlwu.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 00 <unknown>
+
+vlwu.v v8, (a0)
+# CHECK-INST: vlwu.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 02 <unknown>
+
+vlbff.v v8, (a0), v0.t
+# CHECK-INST: vlbff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x11]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 05 11 <unknown>
+
+vlbff.v v8, (a0)
+# CHECK-INST: vlbff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x13]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 05 13 <unknown>
+
+vlhff.v v8, (a0), v0.t
+# CHECK-INST: vlhff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x11]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 05 11 <unknown>
+
+vlhff.v v8, (a0)
+# CHECK-INST: vlhff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x13]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 05 13 <unknown>
+
+vlwff.v v8, (a0), v0.t
+# CHECK-INST: vlwff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x11]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 11 <unknown>
+
+vlwff.v v8, (a0)
+# CHECK-INST: vlwff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x13]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 13 <unknown>
+
+vlbuff.v v8, (a0), v0.t
+# CHECK-INST: vlbuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x04,0x05,0x01]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 05 01 <unknown>
+
+vlbuff.v v8, (a0)
+# CHECK-INST: vlbuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x04,0x05,0x03]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 05 03 <unknown>
+
+vlhuff.v v8, (a0), v0.t
+# CHECK-INST: vlhuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x54,0x05,0x01]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 05 01 <unknown>
+
+vlhuff.v v8, (a0)
+# CHECK-INST: vlhuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x54,0x05,0x03]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 05 03 <unknown>
+
+vlwuff.v v8, (a0), v0.t
+# CHECK-INST: vlwuff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x64,0x05,0x01]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 01 <unknown>
+
+vlwuff.v v8, (a0)
+# CHECK-INST: vlwuff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x64,0x05,0x03]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 05 03 <unknown>
+
+vleff.v v8, (a0), v0.t
+# CHECK-INST: vleff.v v8, (a0), v0.t
+# CHECK-ENCODING: [0x07,0x74,0x05,0x01]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 01 <unknown>
+
+vleff.v v8, (a0)
+# CHECK-INST: vleff.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x05,0x03]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 05 03 <unknown>
+
+vlsb.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsb.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 b5 18 <unknown>
+
+vlsb.v v8, (a0), a1
+# CHECK-INST: vlsb.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 b5 1a <unknown>
+
+vlsh.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsh.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 b5 18 <unknown>
+
+vlsh.v v8, (a0), a1
+# CHECK-INST: vlsh.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 b5 1a <unknown>
+
+vlsw.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsw.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 b5 18 <unknown>
+
+vlsw.v v8, (a0), a1
+# CHECK-INST: vlsw.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 b5 1a <unknown>
+
+vlsbu.v v8, (a0), a1, v0.t
+# CHECK-INST: vlsbu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 b5 08 <unknown>
+
+vlsbu.v v8, (a0), a1
+# CHECK-INST: vlsbu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x04,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 b5 0a <unknown>
+
+vlshu.v v8, (a0), a1, v0.t
+# CHECK-INST: vlshu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 b5 08 <unknown>
+
+vlshu.v v8, (a0), a1
+# CHECK-INST: vlshu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x54,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 b5 0a <unknown>
+
+vlswu.v v8, (a0), a1, v0.t
+# CHECK-INST: vlswu.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 b5 08 <unknown>
+
+vlswu.v v8, (a0), a1
+# CHECK-INST: vlswu.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x64,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 b5 0a <unknown>
+
+vlse.v v8, (a0), a1, v0.t
+# CHECK-INST: vlse.v v8, (a0), a1, v0.t
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 b5 08 <unknown>
+
+vlse.v v8, (a0), a1
+# CHECK-INST: vlse.v v8, (a0), a1
+# CHECK-ENCODING: [0x07,0x74,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 b5 0a <unknown>
+
+vlxb.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxb.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 1c <unknown>
+
+vlxb.v v8, (a0), v4
+# CHECK-INST: vlxb.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 1e <unknown>
+
+vlxh.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxh.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 1c <unknown>
+
+vlxh.v v8, (a0), v4
+# CHECK-INST: vlxh.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 1e <unknown>
+
+vlxw.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxw.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 1c <unknown>
+
+vlxw.v v8, (a0), v4
+# CHECK-INST: vlxw.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 1e <unknown>
+
+vlxbu.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxbu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x04,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 0c <unknown>
+
+vlxbu.v v8, (a0), v4
+# CHECK-INST: vlxbu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x04,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 04 45 0e <unknown>
+
+vlxhu.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxhu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x54,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 0c <unknown>
+
+vlxhu.v v8, (a0), v4
+# CHECK-INST: vlxhu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x54,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 54 45 0e <unknown>
+
+vlxwu.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxwu.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x64,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 0c <unknown>
+
+vlxwu.v v8, (a0), v4
+# CHECK-INST: vlxwu.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x64,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 64 45 0e <unknown>
+
+vlxe.v v8, (a0), v4, v0.t
+# CHECK-INST: vlxe.v v8, (a0), v4, v0.t
+# CHECK-ENCODING: [0x07,0x74,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 45 0c <unknown>
+
+vlxe.v v8, (a0), v4
+# CHECK-INST: vlxe.v v8, (a0), v4
+# CHECK-ENCODING: [0x07,0x74,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 45 0e <unknown>
+
+vl1r.v v8, (a0)
+# CHECK-INST: vl1r.v v8, (a0)
+# CHECK-ENCODING: [0x07,0x74,0x85,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 07 74 85 02 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/macc.s b/llvm/test/MC/RISCV/rvv/macc.s
new file mode 100644
index 000000000000..1092ff5df44d
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/macc.s
@@ -0,0 +1,189 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: vmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xb4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a b4 <unknown>
+
+vmacc.vv v8, v20, v4
+# CHECK-INST: vmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xb6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a b6 <unknown>
+
+vmacc.vx v8, a0, v4, v0.t
+# CHECK-INST: vmacc.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xb4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 b4 <unknown>
+
+vmacc.vx v8, a0, v4
+# CHECK-INST: vmacc.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xb6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 b6 <unknown>
+
+vnmsac.vv v8, v20, v4, v0.t
+# CHECK-INST: vnmsac.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a bc <unknown>
+
+vnmsac.vv v8, v20, v4
+# CHECK-INST: vnmsac.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a be <unknown>
+
+vnmsac.vx v8, a0, v4, v0.t
+# CHECK-INST: vnmsac.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xbc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 bc <unknown>
+
+vnmsac.vx v8, a0, v4
+# CHECK-INST: vnmsac.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xbe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 be <unknown>
+
+vmadd.vv v8, v20, v4, v0.t
+# CHECK-INST: vmadd.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xa4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a a4 <unknown>
+
+vmadd.vv v8, v20, v4
+# CHECK-INST: vmadd.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xa6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a a6 <unknown>
+
+vmadd.vx v8, a0, v4, v0.t
+# CHECK-INST: vmadd.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 a4 <unknown>
+
+vmadd.vx v8, a0, v4
+# CHECK-INST: vmadd.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 a6 <unknown>
+
+vnmsub.vv v8, v20, v4, v0.t
+# CHECK-INST: vnmsub.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a ac <unknown>
+
+vnmsub.vv v8, v20, v4
+# CHECK-INST: vnmsub.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a ae <unknown>
+
+vnmsub.vx v8, a0, v4, v0.t
+# CHECK-INST: vnmsub.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 ac <unknown>
+
+vnmsub.vx v8, a0, v4
+# CHECK-INST: vnmsub.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 ae <unknown>
+
+vwmaccu.vv v8, v20, v4, v0.t
+# CHECK-INST: vwmaccu.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a f0 <unknown>
+
+vwmaccu.vv v8, v20, v4
+# CHECK-INST: vwmaccu.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a f2 <unknown>
+
+vwmaccu.vx v8, a0, v4, v0.t
+# CHECK-INST: vwmaccu.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xf0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 f0 <unknown>
+
+vwmaccu.vx v8, a0, v4
+# CHECK-INST: vwmaccu.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xf2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 f2 <unknown>
+
+vwmacc.vv v8, v20, v4, v0.t
+# CHECK-INST: vwmacc.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xf4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a f4 <unknown>
+
+vwmacc.vv v8, v20, v4
+# CHECK-INST: vwmacc.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xf6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a f6 <unknown>
+
+vwmacc.vx v8, a0, v4, v0.t
+# CHECK-INST: vwmacc.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xf4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 f4 <unknown>
+
+vwmacc.vx v8, a0, v4
+# CHECK-INST: vwmacc.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xf6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 f6 <unknown>
+
+vwmaccsu.vv v8, v20, v4, v0.t
+# CHECK-INST: vwmaccsu.vv v8, v20, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a fc <unknown>
+
+vwmaccsu.vv v8, v20, v4
+# CHECK-INST: vwmaccsu.vv v8, v20, v4
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a fe <unknown>
+
+vwmaccsu.vx v8, a0, v4, v0.t
+# CHECK-INST: vwmaccsu.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xfc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 fc <unknown>
+
+vwmaccsu.vx v8, a0, v4
+# CHECK-INST: vwmaccsu.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xfe]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 fe <unknown>
+
+vwmaccus.vx v8, a0, v4, v0.t
+# CHECK-INST: vwmaccus.vx v8, a0, v4, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xf8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 f8 <unknown>
+
+vwmaccus.vx v8, a0, v4
+# CHECK-INST: vwmaccus.vx v8, a0, v4
+# CHECK-ENCODING: [0x57,0x64,0x45,0xfa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 fa <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/mask.s b/llvm/test/MC/RISCV/rvv/mask.s
new file mode 100644
index 000000000000..d2157bc215bf
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/mask.s
@@ -0,0 +1,165 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vmand.mm v8, v4, v20
+# CHECK-INST: vmand.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 66 <unknown>
+
+vmnand.mm v8, v4, v20
+# CHECK-INST: vmnand.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 76 <unknown>
+
+vmandnot.mm v8, v4, v20
+# CHECK-INST: vmandnot.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x62]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 62 <unknown>
+
+vmxor.mm v8, v4, v20
+# CHECK-INST: vmxor.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 6e <unknown>
+
+vmor.mm v8, v4, v20
+# CHECK-INST: vmor.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x6a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 6a <unknown>
+
+vmnor.mm v8, v4, v20
+# CHECK-INST: vmnor.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x7a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 7a <unknown>
+
+vmornot.mm v8, v4, v20
+# CHECK-INST: vmornot.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x72]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 72 <unknown>
+
+vmxnor.mm v8, v4, v20
+# CHECK-INST: vmxnor.mm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 7e <unknown>
+
+vpopc.m a2, v4, v0.t
+# CHECK-INST: vpopc.m a2, v4, v0.t
+# CHECK-ENCODING: [0x57,0x26,0x48,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 26 48 40 <unknown>
+
+vpopc.m a2, v4
+# CHECK-INST: vpopc.m a2, v4
+# CHECK-ENCODING: [0x57,0x26,0x48,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 26 48 42 <unknown>
+
+vfirst.m a2, v4, v0.t
+# CHECK-INST: vfirst.m a2, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa6,0x48,0x40]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a6 48 40 <unknown>
+
+vfirst.m a2, v4
+# CHECK-INST: vfirst.m a2, v4
+# CHECK-ENCODING: [0x57,0xa6,0x48,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a6 48 42 <unknown>
+
+vmsbf.m v8, v4, v0.t
+# CHECK-INST: vmsbf.m v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x40,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 40 50 <unknown>
+
+vmsbf.m v8, v4
+# CHECK-INST: vmsbf.m v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x40,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 40 52 <unknown>
+
+vmsif.m v8, v4, v0.t
+# CHECK-INST: vmsif.m v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x41,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 41 50 <unknown>
+
+vmsif.m v8, v4
+# CHECK-INST: vmsif.m v8, v4
+# CHECK-ENCODING: [0x57,0xa4,0x41,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 41 52 <unknown>
+
+vmsof.m v8, v4, v0.t
+# CHECK-INST: vmsof.m v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x41,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 41 50 <unknown>
+
+vmsof.m v8, v4
+# CHECK-INST: vmsof.m v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x41,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 41 52 <unknown>
+
+viota.m v8, v4, v0.t
+# CHECK-INST: viota.m v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x48,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 48 50 <unknown>
+
+viota.m v8, v4
+# CHECK-INST: viota.m v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x48,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 48 52 <unknown>
+
+vid.v v8, v0.t
+# CHECK-INST: vid.v v8, v0.t
+# CHECK-ENCODING: [0x57,0xa4,0x08,0x50]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 08 50 <unknown>
+
+vid.v v8
+# CHECK-INST: vid.v v8
+# CHECK-ENCODING: [0x57,0xa4,0x08,0x52]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 a4 08 52 <unknown>
+
+vmcpy.m v8, v4
+# CHECK-INST: vmcpy.m v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x42,0x66]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 42 66 <unknown>
+
+vmclr.m v8
+# CHECK-INST: vmclr.m v8
+# CHECK-ENCODING: [0x57,0x24,0x84,0x6e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 84 6e <unknown>
+
+vmset.m v8
+# CHECK-INST: vmset.m v8
+# CHECK-ENCODING: [0x57,0x24,0x84,0x7e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 84 7e <unknown>
+
+vmnot.m v8, v4
+# CHECK-INST: vmnot.m v8, v4
+# CHECK-ENCODING: [0x57,0x24,0x42,0x76]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 42 76 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/minmax.s b/llvm/test/MC/RISCV/rvv/minmax.s
new file mode 100644
index 000000000000..7759baf35048
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/minmax.s
@@ -0,0 +1,105 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vminu.vv v8, v4, v20, v0.t
+# CHECK-INST: vminu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 10 <unknown>
+
+vminu.vv v8, v4, v20
+# CHECK-INST: vminu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 12 <unknown>
+
+vminu.vx v8, v4, a0, v0.t
+# CHECK-INST: vminu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 10 <unknown>
+
+vminu.vx v8, v4, a0
+# CHECK-INST: vminu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 12 <unknown>
+
+vmin.vv v8, v4, v20, v0.t
+# CHECK-INST: vmin.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x14]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 14 <unknown>
+
+vmin.vv v8, v4, v20
+# CHECK-INST: vmin.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x16]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 16 <unknown>
+
+vmin.vx v8, v4, a0, v0.t
+# CHECK-INST: vmin.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x14]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 14 <unknown>
+
+vmin.vx v8, v4, a0
+# CHECK-INST: vmin.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x16]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 16 <unknown>
+
+vmaxu.vv v8, v4, v20, v0.t
+# CHECK-INST: vmaxu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 18 <unknown>
+
+vmaxu.vv v8, v4, v20
+# CHECK-INST: vmaxu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 1a <unknown>
+
+vmaxu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmaxu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 18 <unknown>
+
+vmaxu.vx v8, v4, a0
+# CHECK-INST: vmaxu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 1a <unknown>
+
+vmax.vv v8, v4, v20, v0.t
+# CHECK-INST: vmax.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 1c <unknown>
+
+vmax.vv v8, v4, v20
+# CHECK-INST: vmax.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 1e <unknown>
+
+vmax.vx v8, v4, a0, v0.t
+# CHECK-INST: vmax.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 1c <unknown>
+
+vmax.vx v8, v4, a0
+# CHECK-INST: vmax.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 1e <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/mul.s b/llvm/test/MC/RISCV/rvv/mul.s
new file mode 100644
index 000000000000..36e3c32b2c8e
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/mul.s
@@ -0,0 +1,201 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vmul.vv v8, v4, v20, v0.t
+# CHECK-INST: vmul.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x94]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 94 <unknown>
+
+vmul.vv v8, v4, v20
+# CHECK-INST: vmul.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x96]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 96 <unknown>
+
+vmul.vx v8, v4, a0, v0.t
+# CHECK-INST: vmul.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x94]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 94 <unknown>
+
+vmul.vx v8, v4, a0
+# CHECK-INST: vmul.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x96]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 96 <unknown>
+
+vmulh.vv v8, v4, v20, v0.t
+# CHECK-INST: vmulh.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 9c <unknown>
+
+vmulh.vv v8, v4, v20
+# CHECK-INST: vmulh.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 9e <unknown>
+
+vmulh.vx v8, v4, a0, v0.t
+# CHECK-INST: vmulh.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 9c <unknown>
+
+vmulh.vx v8, v4, a0
+# CHECK-INST: vmulh.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 9e <unknown>
+
+vmulhu.vv v8, v4, v20, v0.t
+# CHECK-INST: vmulhu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 90 <unknown>
+
+vmulhu.vv v8, v4, v20
+# CHECK-INST: vmulhu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 92 <unknown>
+
+vmulhu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmulhu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x90]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 90 <unknown>
+
+vmulhu.vx v8, v4, a0
+# CHECK-INST: vmulhu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x92]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 92 <unknown>
+
+vmulhsu.vv v8, v4, v20, v0.t
+# CHECK-INST: vmulhsu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x98]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 98 <unknown>
+
+vmulhsu.vv v8, v4, v20
+# CHECK-INST: vmulhsu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x9a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 9a <unknown>
+
+vmulhsu.vx v8, v4, a0, v0.t
+# CHECK-INST: vmulhsu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x98]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 98 <unknown>
+
+vmulhsu.vx v8, v4, a0
+# CHECK-INST: vmulhsu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x9a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 9a <unknown>
+
+vwmul.vv v8, v4, v20, v0.t
+# CHECK-INST: vwmul.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xec]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a ec <unknown>
+
+vwmul.vv v8, v4, v20
+# CHECK-INST: vwmul.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xee]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a ee <unknown>
+
+vwmul.vx v8, v4, a0, v0.t
+# CHECK-INST: vwmul.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xec]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 ec <unknown>
+
+vwmul.vx v8, v4, a0
+# CHECK-INST: vwmul.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xee]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 ee <unknown>
+
+vwmulu.vv v8, v4, v20, v0.t
+# CHECK-INST: vwmulu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a e0 <unknown>
+
+vwmulu.vv v8, v4, v20
+# CHECK-INST: vwmulu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a e2 <unknown>
+
+vwmulu.vx v8, v4, a0, v0.t
+# CHECK-INST: vwmulu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xe0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 e0 <unknown>
+
+vwmulu.vx v8, v4, a0
+# CHECK-INST: vwmulu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xe2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 e2 <unknown>
+
+vwmulsu.vv v8, v4, v20, v0.t
+# CHECK-INST: vwmulsu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xe8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a e8 <unknown>
+
+vwmulsu.vv v8, v4, v20
+# CHECK-INST: vwmulsu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xea]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a ea <unknown>
+
+vwmulsu.vx v8, v4, a0, v0.t
+# CHECK-INST: vwmulsu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xe8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 e8 <unknown>
+
+vwmulsu.vx v8, v4, a0
+# CHECK-INST: vwmulsu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xea]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 ea <unknown>
+
+vsmul.vv v8, v4, v20, v0.t
+# CHECK-INST: vsmul.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 9c <unknown>
+
+vsmul.vv v8, v4, v20
+# CHECK-INST: vsmul.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 9e <unknown>
+
+vsmul.vx v8, v4, a0, v0.t
+# CHECK-INST: vsmul.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x9c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 9c <unknown>
+
+vsmul.vx v8, v4, a0
+# CHECK-INST: vsmul.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 9e <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/mv.s b/llvm/test/MC/RISCV/rvv/mv.s
new file mode 100644
index 000000000000..3bfcce5426d7
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/mv.s
@@ -0,0 +1,63 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vmv.v.v v8, v20
+# CHECK-INST: vmv.v.v v8, v20
+# CHECK-ENCODING: [0x57,0x04,0x0a,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 0a 5e <unknown>
+
+vmv.v.x v8, a0
+# CHECK-INST: vmv.v.x v8, a0
+# CHECK-ENCODING: [0x57,0x44,0x05,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 05 5e <unknown>
+
+vmv.v.i v8, 15
+# CHECK-INST: vmv.v.i v8, 15
+# CHECK-ENCODING: [0x57,0xb4,0x07,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 07 5e <unknown>
+
+vmv.x.s a2, v4
+# CHECK-INST: vmv.x.s a2, v4
+# CHECK-ENCODING: [0x57,0x26,0x40,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 26 40 42 <unknown>
+
+vmv.s.x v8, a0
+# CHECK-INST: vmv.s.x v8, a0
+# CHECK-ENCODING: [0x57,0x64,0x05,0x42]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 05 42 <unknown>
+
+vmv1r.v v8, v4
+# CHECK-INST: vmv1r.v v8, v4
+# CHECK-ENCODING: [0x57,0x34,0x40,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 34 40 9e <unknown>
+
+vmv2r.v v8, v4
+# CHECK-INST: vmv2r.v v8, v4
+# CHECK-ENCODING: [0x57,0xb4,0x40,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 40 9e <unknown>
+
+vmv4r.v v8, v4
+# CHECK-INST: vmv4r.v v8, v4
+# CHECK-ENCODING: [0x57,0xb4,0x41,0x9e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 41 9e <unknown>
+
+vmv8r.v v8, v24
+# CHECK-INST: vmv8r.v v8, v24
+# CHECK-ENCODING: [0x57,0xb4,0x83,0x9f]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 83 9f <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/or.s b/llvm/test/MC/RISCV/rvv/or.s
new file mode 100644
index 000000000000..2201712aed52
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/or.s
@@ -0,0 +1,45 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vor.vv v8, v4, v20, v0.t
+# CHECK-INST: vor.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 28 <unknown>
+
+vor.vv v8, v4, v20
+# CHECK-INST: vor.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 2a <unknown>
+
+vor.vx v8, v4, a0, v0.t
+# CHECK-INST: vor.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 28 <unknown>
+
+vor.vx v8, v4, a0
+# CHECK-INST: vor.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 2a <unknown>
+
+vor.vi v8, v4, 15, v0.t
+# CHECK-INST: vor.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 28 <unknown>
+
+vor.vi v8, v4, 15
+# CHECK-INST: vor.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 2a <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/others.s b/llvm/test/MC/RISCV/rvv/others.s
new file mode 100644
index 000000000000..727230090051
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/others.s
@@ -0,0 +1,141 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vmerge.vvm v8, v4, v20, v0
+# CHECK-INST: vmerge.vvm v8, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 5c <unknown>
+
+vmerge.vxm v8, v4, a0, v0
+# CHECK-INST: vmerge.vxm v8, v4, a0, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 5c <unknown>
+
+vmerge.vim v8, v4, 15, v0
+# CHECK-INST: vmerge.vim v8, v4, 15, v0
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x5c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 5c <unknown>
+
+vslideup.vx v8, v4, a0, v0.t
+# CHECK-INST: vslideup.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 38 <unknown>
+
+vslideup.vx v8, v4, a0
+# CHECK-INST: vslideup.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 3a <unknown>
+
+vslideup.vi v8, v4, 31, v0.t
+# CHECK-INST: vslideup.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f 38 <unknown>
+
+vslideup.vi v8, v4, 31
+# CHECK-INST: vslideup.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f 3a <unknown>
+
+vslidedown.vx v8, v4, a0, v0.t
+# CHECK-INST: vslidedown.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 3c <unknown>
+
+vslidedown.vx v8, v4, a0
+# CHECK-INST: vslidedown.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 3e <unknown>
+
+vslidedown.vi v8, v4, 31, v0.t
+# CHECK-INST: vslidedown.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f 3c <unknown>
+
+vslidedown.vi v8, v4, 31
+# CHECK-INST: vslidedown.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f 3e <unknown>
+
+vslide1up.vx v8, v4, a0, v0.t
+# CHECK-INST: vslide1up.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x38]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 38 <unknown>
+
+vslide1up.vx v8, v4, a0
+# CHECK-INST: vslide1up.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x3a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 3a <unknown>
+
+vslide1down.vx v8, v4, a0, v0.t
+# CHECK-INST: vslide1down.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x3c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 3c <unknown>
+
+vslide1down.vx v8, v4, a0
+# CHECK-INST: vslide1down.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x3e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 3e <unknown>
+
+vrgather.vv v8, v4, v20, v0.t
+# CHECK-INST: vrgather.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x30]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 30 <unknown>
+
+vrgather.vv v8, v4, v20
+# CHECK-INST: vrgather.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 32 <unknown>
+
+vrgather.vx v8, v4, a0, v0.t
+# CHECK-INST: vrgather.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x30]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 30 <unknown>
+
+vrgather.vx v8, v4, a0
+# CHECK-INST: vrgather.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 32 <unknown>
+
+vrgather.vi v8, v4, 31, v0.t
+# CHECK-INST: vrgather.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x30]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f 30 <unknown>
+
+vrgather.vi v8, v4, 31
+# CHECK-INST: vrgather.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x32]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f 32 <unknown>
+
+vcompress.vm v8, v4, v20
+# CHECK-INST: vcompress.vm v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x5e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 5e <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/reduction.s b/llvm/test/MC/RISCV/rvv/reduction.s
new file mode 100644
index 000000000000..dc5adec0a566
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/reduction.s
@@ -0,0 +1,129 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vredsum.vs v8, v4, v20, v0.t
+# CHECK-INST: vredsum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 00 <unknown>
+
+vredsum.vs v8, v4, v20
+# CHECK-INST: vredsum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 02 <unknown>
+
+vredmaxu.vs v8, v4, v20, v0.t
+# CHECK-INST: vredmaxu.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x18]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 18 <unknown>
+
+vredmaxu.vs v8, v4, v20
+# CHECK-INST: vredmaxu.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x1a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 1a <unknown>
+
+vredmax.vs v8, v4, v20, v0.t
+# CHECK-INST: vredmax.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 1c <unknown>
+
+vredmax.vs v8, v4, v20
+# CHECK-INST: vredmax.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 1e <unknown>
+
+vredminu.vs v8, v4, v20, v0.t
+# CHECK-INST: vredminu.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x10]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 10 <unknown>
+
+vredminu.vs v8, v4, v20
+# CHECK-INST: vredminu.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x12]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 12 <unknown>
+
+vredmin.vs v8, v4, v20, v0.t
+# CHECK-INST: vredmin.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x14]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 14 <unknown>
+
+vredmin.vs v8, v4, v20
+# CHECK-INST: vredmin.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x16]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 16 <unknown>
+
+vredand.vs v8, v4, v20, v0.t
+# CHECK-INST: vredand.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x04]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 04 <unknown>
+
+vredand.vs v8, v4, v20
+# CHECK-INST: vredand.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x06]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 06 <unknown>
+
+vredor.vs v8, v4, v20, v0.t
+# CHECK-INST: vredor.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 08 <unknown>
+
+vredor.vs v8, v4, v20
+# CHECK-INST: vredor.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 0a <unknown>
+
+vredxor.vs v8, v4, v20, v0.t
+# CHECK-INST: vredxor.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 0c <unknown>
+
+vredxor.vs v8, v4, v20
+# CHECK-INST: vredxor.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 0e <unknown>
+
+vwredsumu.vs v8, v4, v20, v0.t
+# CHECK-INST: vwredsumu.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xc0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a c0 <unknown>
+
+vwredsumu.vs v8, v4, v20
+# CHECK-INST: vwredsumu.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xc2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a c2 <unknown>
+
+vwredsum.vs v8, v4, v20, v0.t
+# CHECK-INST: vwredsum.vs v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xc4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a c4 <unknown>
+
+vwredsum.vs v8, v4, v20
+# CHECK-INST: vwredsum.vs v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xc6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a c6 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/shift.s b/llvm/test/MC/RISCV/rvv/shift.s
new file mode 100644
index 000000000000..27d40a57a84b
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/shift.s
@@ -0,0 +1,261 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsll.vv v8, v4, v20, v0.t
+# CHECK-INST: vsll.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x94]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 94 <unknown>
+
+vsll.vv v8, v4, v20
+# CHECK-INST: vsll.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x96]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 96 <unknown>
+
+vsll.vx v8, v4, a0, v0.t
+# CHECK-INST: vsll.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x94]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 94 <unknown>
+
+vsll.vx v8, v4, a0
+# CHECK-INST: vsll.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x96]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 96 <unknown>
+
+vsll.vi v8, v4, 31, v0.t
+# CHECK-INST: vsll.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x94]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f 94 <unknown>
+
+vsll.vi v8, v4, 31
+# CHECK-INST: vsll.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x96]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f 96 <unknown>
+
+vsrl.vv v8, v4, v20, v0.t
+# CHECK-INST: vsrl.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a a0 <unknown>
+
+vsrl.vv v8, v4, v20
+# CHECK-INST: vsrl.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a a2 <unknown>
+
+vsrl.vx v8, v4, a0, v0.t
+# CHECK-INST: vsrl.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 a0 <unknown>
+
+vsrl.vx v8, v4, a0
+# CHECK-INST: vsrl.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 a2 <unknown>
+
+vsrl.vi v8, v4, 31, v0.t
+# CHECK-INST: vsrl.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f a0 <unknown>
+
+vsrl.vi v8, v4, 31
+# CHECK-INST: vsrl.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f a2 <unknown>
+
+vsra.vv v8, v4, v20, v0.t
+# CHECK-INST: vsra.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xa4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a a4 <unknown>
+
+vsra.vv v8, v4, v20
+# CHECK-INST: vsra.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xa6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a a6 <unknown>
+
+vsra.vx v8, v4, a0, v0.t
+# CHECK-INST: vsra.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xa4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 a4 <unknown>
+
+vsra.vx v8, v4, a0
+# CHECK-INST: vsra.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xa6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 a6 <unknown>
+
+vsra.vi v8, v4, 31, v0.t
+# CHECK-INST: vsra.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f a4 <unknown>
+
+vsra.vi v8, v4, 31
+# CHECK-INST: vsra.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f a6 <unknown>
+
+vnsrl.wv v8, v4, v20, v0.t
+# CHECK-INST: vnsrl.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a b0 <unknown>
+
+vnsrl.wv v8, v4, v20
+# CHECK-INST: vnsrl.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a b2 <unknown>
+
+vnsrl.wx v8, v4, a0, v0.t
+# CHECK-INST: vnsrl.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 b0 <unknown>
+
+vnsrl.wx v8, v4, a0
+# CHECK-INST: vnsrl.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 b2 <unknown>
+
+vnsrl.wi v8, v4, 31, v0.t
+# CHECK-INST: vnsrl.wi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb0]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f b0 <unknown>
+
+vnsrl.wi v8, v4, 31
+# CHECK-INST: vnsrl.wi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb2]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f b2 <unknown>
+
+vnsra.wv v8, v4, v20, v0.t
+# CHECK-INST: vnsra.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xb4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a b4 <unknown>
+
+vnsra.wv v8, v4, v20
+# CHECK-INST: vnsra.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xb6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a b6 <unknown>
+
+vnsra.wx v8, v4, a0, v0.t
+# CHECK-INST: vnsra.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xb4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 b4 <unknown>
+
+vnsra.wx v8, v4, a0
+# CHECK-INST: vnsra.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xb6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 b6 <unknown>
+
+vnsra.wi v8, v4, 31, v0.t
+# CHECK-INST: vnsra.wi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb4]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f b4 <unknown>
+
+vnsra.wi v8, v4, 31
+# CHECK-INST: vnsra.wi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xb6]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f b6 <unknown>
+
+vssrl.vv v8, v4, v20, v0.t
+# CHECK-INST: vssrl.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a a8 <unknown>
+
+vssrl.vv v8, v4, v20
+# CHECK-INST: vssrl.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a aa <unknown>
+
+vssrl.vx v8, v4, a0, v0.t
+# CHECK-INST: vssrl.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 a8 <unknown>
+
+vssrl.vx v8, v4, a0
+# CHECK-INST: vssrl.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 aa <unknown>
+
+vssrl.vi v8, v4, 31, v0.t
+# CHECK-INST: vssrl.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xa8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f a8 <unknown>
+
+vssrl.vi v8, v4, 31
+# CHECK-INST: vssrl.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xaa]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f aa <unknown>
+
+vssra.vv v8, v4, v20, v0.t
+# CHECK-INST: vssra.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a ac <unknown>
+
+vssra.vv v8, v4, v20
+# CHECK-INST: vssra.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a ae <unknown>
+
+vssra.vx v8, v4, a0, v0.t
+# CHECK-INST: vssra.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 ac <unknown>
+
+vssra.vx v8, v4, a0
+# CHECK-INST: vssra.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 ae <unknown>
+
+vssra.vi v8, v4, 31, v0.t
+# CHECK-INST: vssra.vi v8, v4, 31, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xac]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f ac <unknown>
+
+vssra.vi v8, v4, 31
+# CHECK-INST: vssra.vi v8, v4, 31
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0xae]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f ae <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/sign-injection.s b/llvm/test/MC/RISCV/rvv/sign-injection.s
new file mode 100644
index 000000000000..0831f923be3f
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/sign-injection.s
@@ -0,0 +1,81 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vfsgnj.vv v8, v4, v20, v0.t
+# CHECK-INST: vfsgnj.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 20 <unknown>
+
+vfsgnj.vv v8, v4, v20
+# CHECK-INST: vfsgnj.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 22 <unknown>
+
+vfsgnj.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfsgnj.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x20]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 20 <unknown>
+
+vfsgnj.vf v8, v4, fa0
+# CHECK-INST: vfsgnj.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x22]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 22 <unknown>
+
+vfsgnjn.vv v8, v4, v20, v0.t
+# CHECK-INST: vfsgnjn.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x24]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 24 <unknown>
+
+vfsgnjn.vv v8, v4, v20
+# CHECK-INST: vfsgnjn.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x26]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 26 <unknown>
+
+vfsgnjn.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfsgnjn.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x24]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 24 <unknown>
+
+vfsgnjn.vf v8, v4, fa0
+# CHECK-INST: vfsgnjn.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x26]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 26 <unknown>
+
+vfsgnjx.vv v8, v4, v20, v0.t
+# CHECK-INST: vfsgnjx.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 28 <unknown>
+
+vfsgnjx.vv v8, v4, v20
+# CHECK-INST: vfsgnjx.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x14,0x4a,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 14 4a 2a <unknown>
+
+vfsgnjx.vf v8, v4, fa0, v0.t
+# CHECK-INST: vfsgnjx.vf v8, v4, fa0, v0.t
+# CHECK-ENCODING: [0x57,0x54,0x45,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 28 <unknown>
+
+vfsgnjx.vf v8, v4, fa0
+# CHECK-INST: vfsgnjx.vf v8, v4, fa0
+# CHECK-ENCODING: [0x57,0x54,0x45,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 54 45 2a <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/snippet.s b/llvm/test/MC/RISCV/rvv/snippet.s
new file mode 100644
index 000000000000..fd38631c4ba7
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/snippet.s
@@ -0,0 +1,32 @@
+## A snippet from https://github.com/riscv/riscv-v-spec.
+
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v < %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+
+loop:
+ vsetvli a3, a0, e16,m4 # vtype = 16-bit integer vectors
+# CHECK-INST: d7 76 65 00 vsetvli a3, a0, e16,m4
+ vlh.v v4, (a1) # Get 16b vector
+# CHECK-INST: 07 d2 05 12 vlh.v v4, (a1)
+ slli t1, a3, 1 # Multiply length by two bytes/element
+# CHECK-INST: 13 93 16 00 slli t1, a3, 1
+ add a1, a1, t1 # Bump pointer
+# CHECK-INST: b3 85 65 00 add a1, a1, t1
+ vwmul.vx v8, v4, x10 # 32b in <v8--v15>
+# CHECK-INST: 57 64 45 ee vwmul.vx v8, v4, a0
+
+ vsetvli x0, a0, e32,m8 # Operate on 32b values
+# CHECK-INST: 57 70 b5 00 vsetvli zero, a0, e32,m8
+ vsrl.vi v8, v8, 3
+# CHECK-INST: 57 b4 81 a2 vsrl.vi v8, v8, 3
+ vsw.v v8, (a2) # Store vector of 32b
+# CHECK-INST: 27 64 06 02 vsw.v v8, (a2)
+ slli t1, a3, 2 # Multiply length by four bytes/element
+# CHECK-INST: 13 93 26 00 slli t1, a3, 2
+ add a2, a2, t1 # Bump pointer
+# CHECK-INST: 33 06 66 00 add a2, a2, t1
+ sub a0, a0, a3 # Decrement count
+# CHECK-INST: 33 05 d5 40 sub a0, a0, a3
+ bnez a0, loop # Any more?
+# CHECK-INST: e3 1a 05 fc bnez a0, -44
diff --git a/llvm/test/MC/RISCV/rvv/store.s b/llvm/test/MC/RISCV/rvv/store.s
new file mode 100644
index 000000000000..9d25b593ef82
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/store.s
@@ -0,0 +1,207 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsb.v v24, (a0), v0.t
+# CHECK-INST: vsb.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 05 00 <unknown>
+
+vsb.v v24, (a0)
+# CHECK-INST: vsb.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x0c,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 05 02 <unknown>
+
+vsh.v v24, (a0), v0.t
+# CHECK-INST: vsh.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 05 00 <unknown>
+
+vsh.v v24, (a0)
+# CHECK-INST: vsh.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x5c,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 05 02 <unknown>
+
+vsw.v v24, (a0), v0.t
+# CHECK-INST: vsw.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 05 00 <unknown>
+
+vsw.v v24, (a0)
+# CHECK-INST: vsw.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x6c,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 05 02 <unknown>
+
+vse.v v24, (a0), v0.t
+# CHECK-INST: vse.v v24, (a0), v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 05 00 <unknown>
+
+vse.v v24, (a0)
+# CHECK-INST: vse.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x05,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 05 02 <unknown>
+
+vssb.v v24, (a0), a1, v0.t
+# CHECK-INST: vssb.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c b5 08 <unknown>
+
+vssb.v v24, (a0), a1
+# CHECK-INST: vssb.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x0c,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c b5 0a <unknown>
+
+vssh.v v24, (a0), a1, v0.t
+# CHECK-INST: vssh.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c b5 08 <unknown>
+
+vssh.v v24, (a0), a1
+# CHECK-INST: vssh.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x5c,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c b5 0a <unknown>
+
+vssw.v v24, (a0), a1, v0.t
+# CHECK-INST: vssw.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c b5 08 <unknown>
+
+vssw.v v24, (a0), a1
+# CHECK-INST: vssw.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x6c,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c b5 0a <unknown>
+
+vsse.v v24, (a0), a1, v0.t
+# CHECK-INST: vsse.v v24, (a0), a1, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c b5 08 <unknown>
+
+vsse.v v24, (a0), a1
+# CHECK-INST: vsse.v v24, (a0), a1
+# CHECK-ENCODING: [0x27,0x7c,0xb5,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c b5 0a <unknown>
+
+vsxb.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxb.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 45 0c <unknown>
+
+vsxb.v v24, (a0), v4
+# CHECK-INST: vsxb.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 45 0e <unknown>
+
+vsxh.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxh.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 45 0c <unknown>
+
+vsxh.v v24, (a0), v4
+# CHECK-INST: vsxh.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 45 0e <unknown>
+
+vsxw.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxw.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 45 0c <unknown>
+
+vsxw.v v24, (a0), v4
+# CHECK-INST: vsxw.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 45 0e <unknown>
+
+vsxe.v v24, (a0), v4, v0.t
+# CHECK-INST: vsxe.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 45 0c <unknown>
+
+vsxe.v v24, (a0), v4
+# CHECK-INST: vsxe.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 45 0e <unknown>
+
+vsuxb.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxb.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 45 1c <unknown>
+
+vsuxb.v v24, (a0), v4
+# CHECK-INST: vsuxb.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x0c,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 0c 45 1e <unknown>
+
+vsuxh.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxh.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 45 1c <unknown>
+
+vsuxh.v v24, (a0), v4
+# CHECK-INST: vsuxh.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x5c,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 5c 45 1e <unknown>
+
+vsuxw.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxw.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 45 1c <unknown>
+
+vsuxw.v v24, (a0), v4
+# CHECK-INST: vsuxw.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x6c,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 6c 45 1e <unknown>
+
+vsuxe.v v24, (a0), v4, v0.t
+# CHECK-INST: vsuxe.v v24, (a0), v4, v0.t
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x1c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 45 1c <unknown>
+
+vsuxe.v v24, (a0), v4
+# CHECK-INST: vsuxe.v v24, (a0), v4
+# CHECK-ENCODING: [0x27,0x7c,0x45,0x1e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 45 1e <unknown>
+
+vs1r.v v24, (a0)
+# CHECK-INST: vs1r.v v24, (a0)
+# CHECK-ENCODING: [0x27,0x7c,0x85,0x02]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 27 7c 85 02 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/sub.s b/llvm/test/MC/RISCV/rvv/sub.s
new file mode 100644
index 000000000000..99b0c7a1e60f
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/sub.s
@@ -0,0 +1,285 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsub.vv v8, v4, v20, v0.t
+# CHECK-INST: vsub.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 08 <unknown>
+
+vsub.vv v8, v4, v20
+# CHECK-INST: vsub.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 0a <unknown>
+
+vsub.vx v8, v4, a0, v0.t
+# CHECK-INST: vsub.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x08]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 08 <unknown>
+
+vsub.vx v8, v4, a0
+# CHECK-INST: vsub.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x0a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 0a <unknown>
+
+vrsub.vx v8, v4, a0, v0.t
+# CHECK-INST: vrsub.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 0c <unknown>
+
+vrsub.vx v8, v4, a0
+# CHECK-INST: vrsub.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 0e <unknown>
+
+vrsub.vi v8, v4, 15, v0.t
+# CHECK-INST: vrsub.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x0c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 0c <unknown>
+
+vrsub.vi v8, v4, 15
+# CHECK-INST: vrsub.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x0e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 0e <unknown>
+
+vwsubu.vv v8, v4, v20, v0.t
+# CHECK-INST: vwsubu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xc8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a c8 <unknown>
+
+vwsubu.vv v8, v4, v20
+# CHECK-INST: vwsubu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xca]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a ca <unknown>
+
+vwsubu.vx v8, v4, a0, v0.t
+# CHECK-INST: vwsubu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xc8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 c8 <unknown>
+
+vwsubu.vx v8, v4, a0
+# CHECK-INST: vwsubu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xca]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 ca <unknown>
+
+vwsub.vv v8, v4, v20, v0.t
+# CHECK-INST: vwsub.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xcc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a cc <unknown>
+
+vwsub.vv v8, v4, v20
+# CHECK-INST: vwsub.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xce]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a ce <unknown>
+
+vwsub.vx v8, v4, a0, v0.t
+# CHECK-INST: vwsub.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xcc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 cc <unknown>
+
+vwsub.vx v8, v4, a0
+# CHECK-INST: vwsub.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xce]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 ce <unknown>
+
+vwsubu.wv v8, v4, v20, v0.t
+# CHECK-INST: vwsubu.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xd8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a d8 <unknown>
+
+vwsubu.wv v8, v4, v20
+# CHECK-INST: vwsubu.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xda]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a da <unknown>
+
+vwsubu.wx v8, v4, a0, v0.t
+# CHECK-INST: vwsubu.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xd8]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 d8 <unknown>
+
+vwsubu.wx v8, v4, a0
+# CHECK-INST: vwsubu.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xda]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 da <unknown>
+
+vwsub.wv v8, v4, v20, v0.t
+# CHECK-INST: vwsub.wv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xdc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a dc <unknown>
+
+vwsub.wv v8, v4, v20
+# CHECK-INST: vwsub.wv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0xde]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a de <unknown>
+
+vwsub.wx v8, v4, a0, v0.t
+# CHECK-INST: vwsub.wx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0xdc]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 dc <unknown>
+
+vwsub.wx v8, v4, a0
+# CHECK-INST: vwsub.wx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0xde]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 de <unknown>
+
+vsbc.vvm v8, v4, v20, v0
+# CHECK-INST: vsbc.vvm v8, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 48 <unknown>
+
+vsbc.vxm v8, v4, a0, v0
+# CHECK-INST: vsbc.vxm v8, v4, a0, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x48]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 48 <unknown>
+
+vmsbc.vvm v8, v4, v20, v0
+# CHECK-INST: vmsbc.vvm v8, v4, v20, v0
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x4c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 4c <unknown>
+
+vmsbc.vxm v8, v4, a0, v0
+# CHECK-INST: vmsbc.vxm v8, v4, a0, v0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x4c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 4c <unknown>
+
+vmsbc.vv v8, v4, v20
+# CHECK-INST: vmsbc.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x4e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 4e <unknown>
+
+vmsbc.vx v8, v4, a0
+# CHECK-INST: vmsbc.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x4e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 4e <unknown>
+
+vssubu.vv v8, v4, v20, v0.t
+# CHECK-INST: vssubu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 88 <unknown>
+
+vssubu.vv v8, v4, v20
+# CHECK-INST: vssubu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 8a <unknown>
+
+vssubu.vx v8, v4, a0, v0.t
+# CHECK-INST: vssubu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x88]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 88 <unknown>
+
+vssubu.vx v8, v4, a0
+# CHECK-INST: vssubu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x8a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 8a <unknown>
+
+vssub.vv v8, v4, v20, v0.t
+# CHECK-INST: vssub.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 8c <unknown>
+
+vssub.vv v8, v4, v20
+# CHECK-INST: vssub.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 8e <unknown>
+
+vssub.vx v8, v4, a0, v0.t
+# CHECK-INST: vssub.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x8c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 8c <unknown>
+
+vssub.vx v8, v4, a0
+# CHECK-INST: vssub.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x8e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 8e <unknown>
+
+vasub.vv v8, v4, v20, v0.t
+# CHECK-INST: vasub.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 2c <unknown>
+
+vasub.vv v8, v4, v20
+# CHECK-INST: vasub.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 2e <unknown>
+
+vasub.vx v8, v4, a0, v0.t
+# CHECK-INST: vasub.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 2c <unknown>
+
+vasub.vx v8, v4, a0
+# CHECK-INST: vasub.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 2e <unknown>
+
+vasubu.vv v8, v4, v20, v0.t
+# CHECK-INST: vasubu.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 28 <unknown>
+
+vasubu.vv v8, v4, v20
+# CHECK-INST: vasubu.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x24,0x4a,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 24 4a 2a <unknown>
+
+vasubu.vx v8, v4, a0, v0.t
+# CHECK-INST: vasubu.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x64,0x45,0x28]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 28 <unknown>
+
+vasubu.vx v8, v4, a0
+# CHECK-INST: vasubu.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x64,0x45,0x2a]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 64 45 2a <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/vsetvl.s b/llvm/test/MC/RISCV/rvv/vsetvl.s
new file mode 100644
index 000000000000..784533445f0c
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/vsetvl.s
@@ -0,0 +1,21 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vsetvli a2, a0, e32,m4
+# CHECK-INST: vsetvli a2, a0, e32,m4
+# CHECK-ENCODING: [0x57,0x76,0xa5,0x00]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 a5 00 <unknown>
+
+vsetvl a2, a0, a1
+# CHECK-INST: vsetvl a2, a0, a1
+# CHECK-ENCODING: [0x57,0x76,0xb5,0x80]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 76 b5 80 <unknown>
diff --git a/llvm/test/MC/RISCV/rvv/xor.s b/llvm/test/MC/RISCV/rvv/xor.s
new file mode 100644
index 000000000000..f9c432c8e7dc
--- /dev/null
+++ b/llvm/test/MC/RISCV/rvv/xor.s
@@ -0,0 +1,57 @@
+# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-v %s \
+# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
+# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d --mattr=+experimental-v - \
+# RUN: | FileCheck %s --check-prefix=CHECK-INST
+# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-v %s \
+# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+
+vxor.vv v8, v4, v20, v0.t
+# CHECK-INST: vxor.vv v8, v4, v20, v0.t
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 2c <unknown>
+
+vxor.vv v8, v4, v20
+# CHECK-INST: vxor.vv v8, v4, v20
+# CHECK-ENCODING: [0x57,0x04,0x4a,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 04 4a 2e <unknown>
+
+vxor.vx v8, v4, a0, v0.t
+# CHECK-INST: vxor.vx v8, v4, a0, v0.t
+# CHECK-ENCODING: [0x57,0x44,0x45,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 2c <unknown>
+
+vxor.vx v8, v4, a0
+# CHECK-INST: vxor.vx v8, v4, a0
+# CHECK-ENCODING: [0x57,0x44,0x45,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 44 45 2e <unknown>
+
+vxor.vi v8, v4, 15, v0.t
+# CHECK-INST: vxor.vi v8, v4, 15, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 2c <unknown>
+
+vxor.vi v8, v4, 15
+# CHECK-INST: vxor.vi v8, v4, 15
+# CHECK-ENCODING: [0x57,0xb4,0x47,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 47 2e <unknown>
+
+vnot.v v8, v4, v0.t
+# CHECK-INST: vnot.v v8, v4, v0.t
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x2c]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f 2c <unknown>
+
+vnot.v v8, v4
+# CHECK-INST: vxor.vi v8, v4, -1
+# CHECK-ENCODING: [0x57,0xb4,0x4f,0x2e]
+# CHECK-ERROR: instruction requires the following: 'V' (Vector Instructions)
+# CHECK-UNKNOWN: 57 b4 4f 2e <unknown>
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