[PATCH] D82670: [AArch64][SVE] Bail out of performPostLD1Combine for scalable types

[Kerry McLaughlin via Phabricator via llvm-commits]

kmclaughlin created this revision.
kmclaughlin added reviewers: sdesmalen, c-rhodes, efriedma.
Herald added subscribers: llvm-commits, danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a project: LLVM.

performPostLD1Combine will introduce either a LD1LANEpost
or LD1DUPpost node, which will cause selection failure if the
return type is a scalable vector.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82670

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll


Index: llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/sve-ld-post-inc.ll
@@ -0,0 +1,25 @@
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+; These tests are here to ensure we don't get a selection error caused
+; by performPostLD1Combine, which should bail out if the return
+; type is a scalable vector
+
+define <vscale x 4 x i32> @test_post_ld1_insert(i32* %a, i32** %ptr, i64 %inc) {
+; CHECK-LABEL: test_post_ld1_insert:
+  %load = load i32, i32* %a
+  %ins = insertelement <vscale x 4 x i32> undef, i32 %load, i32 0
+  %gep = getelementptr i32, i32* %a, i64 %inc
+  store i32* %gep, i32** %ptr
+  ret <vscale x 4 x i32> %ins
+}
+
+define <vscale x 2 x double> @test_post_ld1_dup(double* %a, double** %ptr, i64 %inc) {
+; CHECK-LABEL: test_post_ld1_dup:
+  %load = load double, double* %a
+  %dup = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %load)
+  %gep = getelementptr double, double* %a, i64 %inc
+  store double* %gep, double** %ptr
+  ret <vscale x 2 x double> %dup
+}
+
+declare <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double)
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -12375,6 +12375,9 @@
   SelectionDAG &DAG = DCI.DAG;
   EVT VT = N->getValueType(0);
 
+  if (VT.isScalableVector())
+    return SDValue();
+
   unsigned LoadIdx = IsLaneOp ? 1 : 0;
   SDNode *LD = N->getOperand(LoadIdx).getNode();
   // If it is not LOAD, can not do such combine.


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