[PATCH] D82602: [SelectionDAG] don't split branch on logic-of-vector-compares

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: fhahn, efriedma, RKSimon.
Herald added subscribers: hiraditya, kristof.beyls, mcrosier.
Herald added a project: LLVM.

SelectionDAGBuilder converts logic-of-compares into multiple branches based on a boolean TLI setting in isJumpExpensive(). But that probably never considered the pattern of extracted bools from a vector compare - it seems unlikely that we would want to turn vector logic into control-flow.

The motivating x86 reduction case is shown in PR44565:
https://bugs.llvm.org/show_bug.cgi?id=44565
...and that test shows the expected improvement from using pmovmsk codegen.

For AArch64, I modified the test to include an extra op because the simpler test gets transformed by a codegen invocation of SimplifyCFG. I think what we see currently is an improvement, but it might be better if the 'and' was done on the vector unit. Potentially this could use 'addv' or 'addp' instead?


https://reviews.llvm.org/D82602

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
  llvm/test/CodeGen/AArch64/vec-extract-branch.ll
  llvm/test/CodeGen/X86/setcc-logic.ll


Index: llvm/test/CodeGen/X86/setcc-logic.ll
===================================================================
--- llvm/test/CodeGen/X86/setcc-logic.ll
+++ llvm/test/CodeGen/X86/setcc-logic.ll
@@ -323,15 +323,12 @@
 ; CHECK-NEXT:    xorpd %xmm1, %xmm1
 ; CHECK-NEXT:    cmpltpd %xmm0, %xmm1
 ; CHECK-NEXT:    movmskpd %xmm1, %eax
-; CHECK-NEXT:    testb $1, %al
-; CHECK-NEXT:    je .LBB16_3
-; CHECK-NEXT:  # %bb.1:
-; CHECK-NEXT:    shrb %al
-; CHECK-NEXT:    je .LBB16_3
-; CHECK-NEXT:  # %bb.2: # %true
+; CHECK-NEXT:    cmpb $3, %al
+; CHECK-NEXT:    jne .LBB16_2
+; CHECK-NEXT:  # %bb.1: # %true
 ; CHECK-NEXT:    movl $42, %eax
 ; CHECK-NEXT:    retq
-; CHECK-NEXT:  .LBB16_3: # %false
+; CHECK-NEXT:  .LBB16_2: # %false
 ; CHECK-NEXT:    movl $88, %eax
 ; CHECK-NEXT:    retq
   %t1 = fcmp ogt <2 x double> %x, zeroinitializer
Index: llvm/test/CodeGen/AArch64/vec-extract-branch.ll
===================================================================
--- llvm/test/CodeGen/AArch64/vec-extract-branch.ll
+++ llvm/test/CodeGen/AArch64/vec-extract-branch.ll
@@ -6,16 +6,15 @@
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    fcmgt v0.2d, v0.2d, #0.0
 ; CHECK-NEXT:    xtn v0.2s, v0.2d
-; CHECK-NEXT:    fmov w8, s0
-; CHECK-NEXT:    tbz w8, #0, .LBB0_3
-; CHECK-NEXT:  // %bb.1:
 ; CHECK-NEXT:    mov w8, v0.s[1]
-; CHECK-NEXT:    tbz w8, #0, .LBB0_3
-; CHECK-NEXT:  // %bb.2: // %true
+; CHECK-NEXT:    fmov w9, s0
+; CHECK-NEXT:    and w8, w9, w8
+; CHECK-NEXT:    tbz w8, #0, .LBB0_2
+; CHECK-NEXT:  // %bb.1: // %true
 ; CHECK-NEXT:    mov w8, #42
 ; CHECK-NEXT:    sdiv w0, w8, w0
 ; CHECK-NEXT:    ret
-; CHECK-NEXT:  .LBB0_3: // %false
+; CHECK-NEXT:  .LBB0_2: // %false
 ; CHECK-NEXT:    mov w0, #88
 ; CHECK-NEXT:    ret
   %t1 = fcmp ogt <2 x double> %x, zeroinitializer
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -2296,7 +2296,9 @@
 
   // If this is a series of conditions that are or'd or and'd together, emit
   // this as a sequence of branches instead of setcc's with and/or operations.
-  // As long as jumps are not expensive, this should improve performance.
+  // As long as jumps are not expensive (exceptions for multi-use logic ops,
+  // unpredictable branches, and vector extracts because those jumps are likely
+  // expensive for any target), this should improve performance.
   // For example, instead of something like:
   //     cmp A, B
   //     C = seteq
@@ -2313,7 +2315,9 @@
     Instruction::BinaryOps Opcode = BOp->getOpcode();
     if (!DAG.getTargetLoweringInfo().isJumpExpensive() && BOp->hasOneUse() &&
         !I.hasMetadata(LLVMContext::MD_unpredictable) &&
-        (Opcode == Instruction::And || Opcode == Instruction::Or)) {
+        (Opcode == Instruction::And || Opcode == Instruction::Or) &&
+        !isa<ExtractElementInst>(BOp->getOperand(0)) &&
+        !isa<ExtractElementInst>(BOp->getOperand(1))) {
       FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB,
                            Opcode,
                            getEdgeProbability(BrMBB, Succ0MBB),


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