[PATCH] D82551: [AMDGPU] Don't combine DPP if DPP register is used more than once per instruction

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin marked an inline comment as done.
vpykhtin added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp:359
+  // see defusechain_iterator::operator++
+  if (!Uses.empty() && Uses.back()->getParent() == Use->getParent()) {
+    LLVM_DEBUG(
----------------
rampitec wrote:
> vpykhtin wrote:
> > rampitec wrote:
> > > I assume this exploits the fact we have no instructions which may have more than two uses and are dpp combinable at the same time? If so it deserves a comment.
> > I'm not sure what do you mean - DPP extension can only be applied to src0 operand.
> > 
> > addUse is called in the order of defuse chain traversal: defusechain_iterator::operator++ assumes that all per instruction uses comes continuosly - so I decided to assume the same.
> Hm... This looks like a hack to me.
It's a cornerstone for MachineRegisterInfo's use_instr_.. iterators, otherwise it wouldn't be cheap to walk.


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https://reviews.llvm.org/D82551