[PATCH] D82551: [AMDGPU] Don't combine DPP if DPP register is used more than once per instruction

[Valery Pykhtin via Phabricator via llvm-commits]

vpykhtin created this revision.
vpykhtin added reviewers: arsenm, rampitec, foad.
Herald added subscribers: llvm-commits, kerbowa, kbarton, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, nemanjai, kzhuravl.
Herald added a project: LLVM.

Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82551

Files:
  llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
  llvm/test/CodeGen/AMDGPU/dpp_combine.mir


Index: llvm/test/CodeGen/AMDGPU/dpp_combine.mir
===================================================================
--- llvm/test/CodeGen/AMDGPU/dpp_combine.mir
+++ llvm/test/CodeGen/AMDGPU/dpp_combine.mir
@@ -833,3 +833,33 @@
     S_ENDPGM 0, implicit %4
 
 ...
+
+# GCN-LABEL: name: dont_combine_more_than_one_operand
+# GCN: %3:vgpr_32 = V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec
+name: dont_combine_more_than_one_operand
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1
+    %0:vgpr_32 = COPY $vgpr0
+    %1:vgpr_32 = COPY $vgpr1
+    %2:vgpr_32 = V_MOV_B32_dpp %0, %1, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MAX_F32_e64 0, %2, 0, %2, 0, 0, implicit $mode, implicit $exec
+...
+
+# GCN-LABEL: name: dont_combine_more_than_one_operand_dpp_reg_sequence
+# GCN: %5:vgpr_32 = V_ADD_I32_e32 %4.sub0, %4.sub0, implicit-def $vcc, implicit $exec
+# GCN: %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
+name: dont_combine_more_than_one_operand_dpp_reg_sequence
+tracksRegLiveness: true
+body: |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    %0:vreg_64 = COPY $vgpr0_vgpr1
+    %1:vreg_64 = COPY $vgpr2_vgpr3
+    %2:vgpr_32 = V_MOV_B32_dpp %0.sub0, %1.sub0, 1, 15, 15, 1, implicit $exec
+    %3:vgpr_32 = V_MOV_B32_dpp %0.sub1, %1.sub1, 1, 15, 15, 1, implicit $exec
+    %4:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1
+    %5:vgpr_32 = V_ADD_I32_e32 %4.sub0, %4.sub0, implicit-def $vcc, implicit $exec
+    %6:vgpr_32 = V_ADDC_U32_e32 %4.sub1, %4.sub1, implicit-def $vcc, implicit $vcc, implicit $exec
+...
Index: llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
+++ llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
@@ -352,6 +352,21 @@
   return (Imm->getImm() & Mask) == Value;
 }
 
+static bool addUse(MachineOperand *Use,
+                   SmallVectorImpl<MachineOperand *> &Uses) {
+  // Assuming per instruction uses come together,
+  // see defusechain_iterator::operator++
+  if (!Uses.empty() && Uses.back()->getParent() == Use->getParent()) {
+    LLVM_DEBUG(
+        dbgs()
+        << "  " << *Use->getParent()
+        << "  failed: DPP register is used more than once per instruction\n");
+    return false;
+  }
+  Uses.push_back(Use);
+  return true;
+}
+
 bool GCNDPPCombine::combineDPPMov(MachineInstr &MovMI) const {
   assert(MovMI.getOpcode() == AMDGPU::V_MOV_B32_dpp);
   LLVM_DEBUG(dbgs() << "\nDPP combine: " << MovMI);
@@ -449,7 +464,8 @@
   SmallVector<MachineOperand*, 16> Uses;
 
   for (auto &Use : MRI->use_nodbg_operands(DPPMovReg)) {
-    Uses.push_back(&Use);
+    if (!addUse(&Use, Uses))
+      return false;
   }
 
   while (!Uses.empty()) {
@@ -481,10 +497,16 @@
       if (!FwdSubReg)
         break;
 
+      bool FailedToAddUse = false;
       for (auto &Op : MRI->use_nodbg_operands(FwdReg)) {
         if (Op.getSubReg() == FwdSubReg)
-          Uses.push_back(&Op);
+          if (!addUse(&Op, Uses)) {
+            FailedToAddUse = true;
+            break;
+          }
       }
+      if (FailedToAddUse)
+        break;
       RegSeqWithOpNos[&OrigMI].push_back(OpNo);
       continue;
     }


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