[PATCH] D82510: [PowerPC][Power10] Implement low-order Vector Multiply, Modulus and Divide Instructions

[Amy Kwan via Phabricator via llvm-commits]

amyk created this revision.
amyk added reviewers: power-llvm-team, nemanjai, lei, saghir, PowerPC.
amyk added projects: LLVM, PowerPC.
Herald added subscribers: shchenz, hiraditya.

This patch aims to implement the low order vector multiply, divide and modulo instructions
available on Power10.

The patch involves legalizing the ISD nodes `MUL`, `UDIV`, `SDIV`, `UREM` and `SREM` for 
`v2i64` and `v4i32` vector types in order to utilize the following instructions:

  vmulld VRT, VRA, VRB
  vmodsw VRT, VRA, VRB
  vmoduw VRT, VRA, VRB
  vmodsd VRT, VRA, VRB
  vmodud VRT, VRA, VRB
  vdivsw VRT, VRA, VRB
  vdivuw VRT, VRA, VRB
  vdivsd VRT, VRA, VRB
  vdivud VRT, VRA, VRB


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82510

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/lib/Target/PowerPC/PPCInstrPrefix.td
  llvm/test/CodeGen/PowerPC/p10-vector-divide.ll
  llvm/test/CodeGen/PowerPC/p10-vector-modulo.ll
  llvm/test/CodeGen/PowerPC/p10-vector-multiply.ll

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