[PATCH] D82440: [Power10] Implement Vector Shift Double Bit Immediate Builtins in LLVM/Clang

[Amy Kwan via Phabricator via llvm-commits]

amyk requested changes to this revision.
amyk added inline comments.
This revision now requires changes to proceed.


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Comment at: clang/test/CodeGen/builtins-ppc-p10vector.c:89
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_sldb(vsca, vscb, 0);
+}
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`SH` can be any integer value between 0 and 7. It is better to add some checking to make sure the immediate is between these values.


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Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:181
+// VN-Form: [PO VRT VRA VRB PS SD XO]
+// SD is "Shift Direction" .
+class VNForm_VTAB5_SD3<bits<6> xo, bits<2> ps, dag OOL, dag IOL, string asmstr,
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Nit: Remove the extra space before the `.`


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Comment at: llvm/lib/Target/PowerPC/PPCInstrPrefix.td:581
+   def VSRDBI :
+     VNForm_VTAB5_SD3<22, 0, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB, u3imm:$SH),
+                      "vsrdbi $VRT, $VRA, $VRB, $SH", IIC_VecGeneral,
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The second value (`ps`) should not be 0. It should be 1, right?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82440/new/

https://reviews.llvm.org/D82440