[PATCH] D82439: [ARM] Rearrange SizeReduction when using -Oz

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

In D82439#2112588 <https://reviews.llvm.org/D82439#2112588>, @efriedma wrote:

> You mean, the scheduling models don't handle Thumb1 instructions well?  Or there an issue with the way the actual CPUs handle Thumb1 instructions?


The models do not handle thumb1 instructions well because they have not come up when scheduling in the past. You can (I presume) always treat them just like the equivalent thumb2 instruction and get similar results, but it would take time to get right.

The cores can often dual issue certain combinations of thumb1 instructions, so properly scheduling them would be useful. We currently, especially pre-ra, have to try and guess at what might become a thumb1 instruction. For older cores this wasn't super interesting due to the exact instructions that could be dual issued but newer cores are always getting better. It is on my list to potentially do something about this, if I can find enough cases of it going wrong to make it look promising, seeing as it's only post-ra that we can easily fix.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D82439/new/

https://reviews.llvm.org/D82439