[PATCH] D82215: [AMDGPU] Avoid redundant mode register writes

[Tim Corringham via Phabricator via llvm-commits]

timcorringham marked 3 inline comments as done.
timcorringham added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIModeRegister.cpp:202-206
     BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32))
         .addImm(Value)
         .addImm(((Width - 1) << AMDGPU::Hwreg::WIDTH_M1_SHIFT_) |
                 (Offset << AMDGPU::Hwreg::OFFSET_SHIFT_) |
                 (AMDGPU::Hwreg::ID_MODE << AMDGPU::Hwreg::ID_SHIFT_));
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arsenm wrote:
> This should use the encode function from utils for this, but that's a separate cleanup I guess (plus try to use the new gfx10 instruction)
Planned for a future change.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D82215/new/

https://reviews.llvm.org/D82215