[PATCH] D82443: [ARM] Narrowing half-precision lowering to supported CCs

[Lucas Prates via Phabricator via llvm-commits]

pratlucas added a comment.

Taking a further look to the differences in the DAG, the resulting type is actually the same.
Both result in an `f32` value, but get to it in different ways as expected.

With `ARMTargetLowering::splitValueIntoRegisterParts`:

  t22: f32 = bitcast t21
    t21: i32 = any_extend t20
      t20: i16 = bitcast t5
        t5: f16 = extract_vector_elt t3, Constant:i32<0>
          t3: v8f16,v8f16 = merge_values t2, t2
            t2: v8f16 = BUILD_VECTOR ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f
  16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>

Without `ARMTargetLowering::splitValueIntoRegisterParts`:

  t20: f32 = fp_extend t5
    t5: f16 = extract_vector_elt t3, Constant:i32<0>
      t3: v8f16,v8f16 = merge_values t2, t2
        t2: v8f16 = BUILD_VECTOR ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<A
  PFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>

I'm taking a deeper look into the assertion failure stack to figure out what's causing it.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D82443/new/

https://reviews.llvm.org/D82443