[PATCH] D82443: [ARM] Narrowing half-precision lowering to supported CCs

[Puyan Lotfi via Phabricator via llvm-commits]

plotfi created this revision.
plotfi added reviewers: pratlucas, rjmccall.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.

I had noticed an assert in the ARM backend on builds of the Swift stdlib. I've since reduced the offending IR and reported my findings to the folks on D75169 <https://reviews.llvm.org/D75169>. I suspect that the changes in D75169 <https://reviews.llvm.org/D75169> were meant mainly for the AAPCS calling conventions and indeed they do work fine with them, but with fastcc and swiftcc I noticed there was a crash.

I also noticed that the line that checks the calling convention in D75169 <https://reviews.llvm.org/D75169> is only checking to see that there is a calling convention, not specifically checking that it is a supported calling convention. So this patch does just that, and includes a regression test too.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D82443

Files:
  llvm/lib/Target/ARM/ARMISelLowering.cpp
  llvm/test/CodeGen/ARM/arm-half-promote.ll


Index: llvm/test/CodeGen/ARM/arm-half-promote.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/ARM/arm-half-promote.ll
@@ -0,0 +1,20 @@
+; RUN: llc -mtriple=thumbv7s-apple-ios7.0.0 %s -o -
+
+target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
+target triple = "thumbv7s-apple-ios7.0.0"
+
+define fastcc { <8 x half>, <8 x half> } @f1() {
+  ret { <8 x half>, <8 x half> } zeroinitializer
+}
+
+define arm_aapcscc { <8 x half>, <8 x half> } @f2() {
+  ret { <8 x half>, <8 x half> } zeroinitializer
+}
+
+define arm_apcscc { <8 x half>, <8 x half> } @f3() {
+  ret { <8 x half>, <8 x half> } zeroinitializer
+}
+
+define swiftcc { <8 x half>, <8 x half> } @f4() {
+  ret { <8 x half>, <8 x half> } zeroinitializer
+}
Index: llvm/lib/Target/ARM/ARMISelLowering.cpp
===================================================================
--- llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -4152,7 +4152,12 @@
 bool ARMTargetLowering::splitValueIntoRegisterParts(
     SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts,
     unsigned NumParts, MVT PartVT, Optional<CallingConv::ID> CC) const {
-  bool IsABIRegCopy = CC.hasValue();
+  bool IsABIRegCopy = false;
+  if (CC.hasValue()) {
+    auto CCVal = CC.getValue();
+    IsABIRegCopy =
+        (CCVal == CallingConv::ARM_APCS || CCVal == CallingConv::ARM_AAPCS);
+  }
   EVT ValueVT = Val.getValueType();
   if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
       PartVT == MVT::f32) {
@@ -4170,7 +4175,12 @@
 SDValue ARMTargetLowering::joinRegisterPartsIntoValue(
     SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts,
     MVT PartVT, EVT ValueVT, Optional<CallingConv::ID> CC) const {
-  bool IsABIRegCopy = CC.hasValue();
+  bool IsABIRegCopy = false;
+  if (CC.hasValue()) {
+    auto CCVal = CC.getValue();
+    IsABIRegCopy =
+        (CCVal == CallingConv::ARM_APCS || CCVal == CallingConv::ARM_AAPCS);
+  }
   if (IsABIRegCopy && (ValueVT == MVT::f16 || ValueVT == MVT::bf16) &&
       PartVT == MVT::f32) {
     unsigned ValueBits = ValueVT.getSizeInBits();


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