[PATCH] D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend

[Puyan Lotfi via Phabricator via llvm-commits]

plotfi added a comment.

@pratlucas @ostannard @rjmccall

I have noticed this change break on the building of the Swift standard library in downstream apple/swift/master-next. I reduced the test case and found that the chain of bitcasts/extends in ARMTargetLowering::splitValueIntoRegisterParts ends up not being legal and causing an assert in SelectionDag.cpp when compiling the following with llc:

  target datalayout = "e-m:o-p:32:32-Fi8-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
  target triple = "thumbv7s-apple-ios7.0.0"
  
  define fastcc { <8 x half>, <8 x half> } @f() {
    ret { <8 x half>, <8 x half> } zeroinitializer
  }

This was originally swiftcc, but I changed it to fastcc so it would compile with upstream llvm.org/main while also having a calling convention that would satisfy the conditional here: https://github.com/llvm/llvm-project/blob/bfec030e69afc73b29aa1b66902ae802a448fc19/llvm/lib/Target/ARM/ARMISelLowering.cpp#L4155

The assert is as follows:

  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1307: llvm::SDValue llvm::SelectionDAG::getConstant(const llvm::ConstantInt &, const llvm::SDLoc &, llvm::EVT, bool, bool): Assertion `Elt->getBitWidth() == EltVT.getSizeInBits() && "APInt size does not match type size!"' failed.

The DAG nodes generated before:

  t5: f16 = extract_vector_elt t3, Constant:i32<0>
    t3: v8f16,v8f16 = merge_values t2, t2
      t2: v8f16 = BUILD_VECTOR ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>

And After:

  t22: f32 = bitcast t21
    t21: i32 = any_extend t20
      t20: i16 = bitcast t5
        t5: f16 = extract_vector_elt t3, Constant:i32<0>
          t3: v8f16,v8f16 = merge_values t2, t2
            t2: v8f16 = BUILD_VECTOR ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>, ConstantFP:f16<APFloat(0)>

I suspect here there could be a the EltVT in the assert was expecting a 16-bit size, but is now getting 32.

I hope this is helpful.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75169/new/

https://reviews.llvm.org/D75169