[PATCH] D82202: [AMDGPU] Return restricted number of regs from TTI
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 23 11:49:09 PDT 2020
rampitec marked an inline comment as done.
rampitec added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.cpp:251
+unsigned GCNTTIImpl::getNumberOfRegisters(unsigned RCID) const {
+ const SIRegisterInfo *TRI = ST->getRegisterInfo();
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arsenm wrote:
> Surfacing the reg class ID to IR passes seems problematic
It is already in TTI, we just do not implement it.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82202/new/
https://reviews.llvm.org/D82202
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