[PATCH] D82401: [NFC] Remove assert from SelectionDAG::getZeroExtendInReg

[Jessica Paquette via Phabricator via llvm-commits]

paquette created this revision.
paquette added reviewers: t.p.northover, craig.topper.
Herald added subscribers: hiraditya, kristof.beyls.
Herald added a reviewer: rengolin.
Herald added a project: LLVM.

Remove the assert from `SelectionDAG::getZeroExtendInReg` which checks that `OpVT.isVector() == VT.isVector()`.

This assert was added in c41685b16fcceaa2078eb14eb27f6696f851eb49 <https://reviews.llvm.org/rGc41685b16fcceaa2078eb14eb27f6696f851eb49>. This did some refactoring to reduce the number of calls to `getScalarType`.

If you're building stuff for arm64_32, it's possible to break this assumption.

E.g. in `SelectionDAGBuilder::visitGetElementPtr`:

  MVT PtrTy = TLI.getPointerTy(DAG.getDataLayout(), AS);
  MVT PtrMemTy = TLI.getPointerMemTy(DAG.getDataLayout(), AS);
  ...
  if (PtrMemTy != PtrTy && !cast<GEPOperator>(I).isInBounds())
    N = DAG.getPtrExtendInReg(N, dl, PtrMemTy);

All `getPtrExtendInReg` does is return `getZeroExtendInReg`. So, if `N` is a vector, we'll hit the assert.

Add a testcase to arm64_32-pointer-extend.ll that shows an example of this.


https://reviews.llvm.org/D82401

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AArch64/arm64_32-pointer-extend.ll


Index: llvm/test/CodeGen/AArch64/arm64_32-pointer-extend.ll
===================================================================
--- llvm/test/CodeGen/AArch64/arm64_32-pointer-extend.ll
+++ llvm/test/CodeGen/AArch64/arm64_32-pointer-extend.ll
@@ -47,3 +47,11 @@
   %res = inttoptr i32 %sum32 to i8*
   ret i8* %res
 }
+
+define <2 x i8*> @gep_with_vector() {
+; CHECK-LABEL: gep_with_vector:
+; CHECK: movi.2d	v0, #0000000000000000
+; CHECK-NEXT: ret
+  %vec = getelementptr i8, <2 x i8*> undef, <2 x i32> <i32 42, i32 42>
+  ret <2 x i8*> %vec
+}
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1171,9 +1171,6 @@
   EVT OpVT = Op.getValueType();
   assert(VT.isInteger() && OpVT.isInteger() &&
          "Cannot getZeroExtendInReg FP types");
-  assert(VT.isVector() == OpVT.isVector() &&
-         "getZeroExtendInReg type should be vector iff the operand "
-         "type is vector!");
   assert((!VT.isVector() ||
           VT.getVectorElementCount() == OpVT.getVectorElementCount()) &&
          "Vector element counts must match in getZeroExtendInReg");


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