[PATCH] D82215: [AMDGPU] Avoid redundant mode register writes

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIModeRegister.cpp:136
 
+  bool SetregInserted = false;
+
----------------
Probably should rename this, since this really should try to use S_ROUND_MODE/S_DENORM_MODE


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Comment at: llvm/lib/Target/AMDGPU/SIModeRegister.cpp:202-206
     BuildMI(MBB, MI, 0, TII->get(AMDGPU::S_SETREG_IMM32_B32))
         .addImm(Value)
         .addImm(((Width - 1) << AMDGPU::Hwreg::WIDTH_M1_SHIFT_) |
                 (Offset << AMDGPU::Hwreg::OFFSET_SHIFT_) |
                 (AMDGPU::Hwreg::ID_MODE << AMDGPU::Hwreg::ID_SHIFT_));
----------------
This should use the encode function from utils for this, but that's a separate cleanup I guess (plus try to use the new gfx10 instruction)


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Comment at: llvm/test/CodeGen/AMDGPU/mode-register.mir:464-465
+# CHECK-LABEL: name: single_block_loop
+# CHECK-LABEL: bb.0:
+# CHECK-NOT: S_SETREG
+
----------------
CHECK-NOT can be fragile. The case is so small I would generate the checks


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D82215