[PATCH] D80385: [SVE] Code generation for fixed length vector loads & stores.

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm marked 6 inline comments as done.
paulwalker-arm added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:989
+    if (Src.getValueType().isScalableVector())
+      break;
     SDValue Sub = Op.getOperand(1);
----------------
efriedma wrote:
> This shouldn't be reachable; the type of src is the same as the type of the result.
Yep, looks like I don't need this after the rebase. Thanks, I'll remove it.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:2477
+    if (Src.getValueType().isScalableVector())
+      break;
     SDValue Sub = Op.getOperand(1);
----------------
efriedma wrote:
> Also shouldn't be reachable.
Also removed.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14766
+  // use AArch64SVEPredPattern::all, which can enable the use of unpredicated
+  // variants of instructions when available.
+
----------------
efriedma wrote:
> Could we use the unpredicated variants even if they work on "extra" bits?  It doesn't really matter if an add runs on unused elements.  Many of the unpredicated instructions work like this.  Maybe this doesn't work for certain instructions.
Yes, like you said, it comes down to the instruction.  For example, we'll have to be careful with floating point.  This just gives us a route to be explicit when we know unpredicted instructions are a safe possibility.

It also helps for cases like mul where SVE only has a predicated form but SVE2 adds an unpredicated variant.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80385/new/

https://reviews.llvm.org/D80385