[PATCH] D80385: [SVE] Code generation for fixed length vector loads & stores.

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:989
+    if (Src.getValueType().isScalableVector())
+      break;
     SDValue Sub = Op.getOperand(1);
----------------
This shouldn't be reachable; the type of src is the same as the type of the result.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:2477
+    if (Src.getValueType().isScalableVector())
+      break;
     SDValue Sub = Op.getOperand(1);
----------------
Also shouldn't be reachable.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14766
+  // use AArch64SVEPredPattern::all, which can enable the use of unpredicated
+  // variants of instructions when available.
+
----------------
Could we use the unpredicated variants even if they work on "extra" bits?  It doesn't really matter if an add runs on unused elements.  Many of the unpredicated instructions work like this.  Maybe this doesn't work for certain instructions.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80385/new/

https://reviews.llvm.org/D80385