[PATCH] D68667: [SLP] respect target register width for GEP vectorization (PR43578)

Mon Jun 22 11:17:14 PDT 2020

spatel added a comment.

In D68667#2107079 <https://reviews.llvm.org/D68667#2107079>, @fhahn wrote:

> In D68667#2106962 <https://reviews.llvm.org/D68667#2106962>, @fhahn wrote:
>
> > I tracked down a 7% regression in h264  on AArch64 -O3 LTO & PGO to this commit. The regressions in the aarch64 tests seem a bit suspicious and from the description the changes seem unintentional (4 x i32 vectors should be perfectly legal on AArch64). I'll take a look to see what's going on.
>
>
> Oh I now see what's going on. The actual compute is done on i64 x 4.

But not in the getelementptr_4x32() test, right? Maybe we need to refine getVectorElementSize() in some way.

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https://reviews.llvm.org/D68667