[PATCH] D68667: [SLP] respect target register width for GEP vectorization (PR43578)

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

I tracked down a 7% regression in h264  on AArch64 -O3 LTO & PGO to this commit. The regressions in the aarch64 tests seem a bit suspicious and from the description the changes seem unintentional (4 x i32 vectors should be perfectly legal on AArch64). I'll take a look to see what's going on.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D68667/new/

https://reviews.llvm.org/D68667