[PATCH] D80741: [llvm][SVE] Reg + reg addressing mode for LD1RO.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli updated this revision to Diff 271909.
fpetrogalli added a comment.

Added the bfloat test case that was missing.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80741/new/

https://reviews.llvm.org/D80741

Files:
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro-addressing-mode-reg-reg.ll

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