[PATCH] D80741: [llvm][SVE] Reg + reg addressing mode for LD1RO.

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.
This revision is now accepted and ready to land.

LGTM



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Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-ld1ro-addressing-mode-reg-reg.ll:80
+  ret <vscale x 2 x double> %load
+}
+
----------------
fpetrogalli wrote:
> efriedma wrote:
> > I'd like to see a couple testcases where the pattern doesn't match; wrong shift, or subtraction, or something like that
> Isn't this covered by the tests in https://reviews.llvm.org/D80738? Those tests are saying: "default to `[xBASE]` if you cannot figure out an optimal addressing mode supported by the instruction". Or am I missing something?
D80738 covers the general possibility that there is no match, but it doesn't really verify that am_sve_regreg_lsl1 is doing the right thing in non-trivial cases.  I guess we have coverage from other instructions, though.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80741/new/

https://reviews.llvm.org/D80741