[llvm] 3f0c9c1 - Fix ubsan error in tblgen with signed left shift

[Stanislav Mekhanoshin via llvm-commits]

Author: Stanislav Mekhanoshin
Date: 2020-06-16T11:15:09-07:00
New Revision: 3f0c9c1634237834af6b74e9319cb15f6ab89d11

URL: https://github.com/llvm/llvm-project/commit/3f0c9c1634237834af6b74e9319cb15f6ab89d11
DIFF: https://github.com/llvm/llvm-project/commit/3f0c9c1634237834af6b74e9319cb15f6ab89d11.diff

LOG: Fix ubsan error in tblgen with signed left shift

UBSAN complains when tblgen performs SHL of a negative
value.

Differential Revision: https://reviews.llvm.org/D81952

Added: 
    

Modified: 
    llvm/lib/TableGen/Record.cpp
    llvm/lib/Target/AMDGPU/SMInstructions.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp
index 50df5daaf4c1..d3db004196b8 100644
--- a/llvm/lib/TableGen/Record.cpp
+++ b/llvm/lib/TableGen/Record.cpp
@@ -1030,7 +1030,7 @@ Init *BinOpInit::Fold(Record *CurRec) const {
       case MUL: Result = LHSv *  RHSv; break;
       case AND: Result = LHSv &  RHSv; break;
       case OR: Result = LHSv | RHSv; break;
-      case SHL: Result = LHSv << RHSv; break;
+      case SHL: Result = (uint64_t)LHSv << (uint64_t)RHSv; break;
       case SRA: Result = LHSv >> RHSv; break;
       case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break;
       }

diff  --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index df21c864ccad..252f191a2f66 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -860,7 +860,7 @@ let OtherPredicates = [HasNoSMemTimeInst] in {
 def : GCNPat <
   (i64 (readcyclecounter)),
   (REG_SEQUENCE SReg_64,
-    (S_GETREG_B32 -26595), sub0,
+    (S_GETREG_B32 getHwRegImm<HWREG.SHADER_CYCLES, 0, -12>.ret), sub0,
     (S_MOV_B32 (i32 0)), sub1)
 >;
 } // let OtherPredicates = [HasNoSMemTimeInst]