[llvm] 576fa5a - [AMDGPU] make ubsan happy with unsigned left shift

[Mekhanoshin, Stanislav via llvm-commits]

[AMD Official Use Only - Internal Distribution Only]

I need to figure it out. It is tablegen produced some C++ code, which in turn resulted in UB. At the moment I have just put the constant there to clear the testing, the actual expected behavior is still questionable. It was !shl($var, 11) and the $var was negative. So it is a shift of a negative value. I do not see any issue with the shl of a negative value in 2-complement off hand given the size is the same size.

Stas

From: Arsenault, Matthew <Matthew.Arsenault at amd.com>
Sent: Monday, June 15, 2020 17:28
To: llvm-commits at lists.llvm.org; Mekhanoshin, Stanislav <Stanislav.Mekhanoshin at amd.com>; Stanislav Mekhanoshin <llvmlistbot at llvm.org>
Subject: Re: [llvm] 576fa5a - [AMDGPU] make ubsan happy with unsigned left shift


[AMD Official Use Only - Internal Distribution Only]

This was in the tabelgen shift? Tablegen should be fixed instead?

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From: llvm-commits <llvm-commits-bounces at lists.llvm.org<mailto:llvm-commits-bounces at lists.llvm.org>> on behalf of Stanislav Mekhanoshin via llvm-commits <llvm-commits at lists.llvm.org<mailto:llvm-commits at lists.llvm.org>>
Sent: Monday, June 15, 2020 5:21 PM
To: llvm-commits at lists.llvm.org<mailto:llvm-commits at lists.llvm.org> <llvm-commits at lists.llvm.org<mailto:llvm-commits at lists.llvm.org>>
Subject: [llvm] 576fa5a - [AMDGPU] make ubsan happy with unsigned left shift


Author: Stanislav Mekhanoshin
Date: 2020-06-15T17:21:10-07:00
New Revision: 576fa5a50c8509977835031d190f8906e1dbb075

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LOG: [AMDGPU] make ubsan happy with unsigned left shift

Fixes UBSAN error after rG9ee272f13d88f090817235ef4f91e56bb2a153d6
A trivial signed/unsigned shift.

Added:


Modified:
    llvm/lib/Target/AMDGPU/SMInstructions.td

Removed:



################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 252f191a2f66..df21c864ccad 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -860,7 +860,7 @@ let OtherPredicates = [HasNoSMemTimeInst] in {
 def : GCNPat <
   (i64 (readcyclecounter)),
   (REG_SEQUENCE SReg_64,
-    (S_GETREG_B32 getHwRegImm<HWREG.SHADER_CYCLES, 0, -12>.ret), sub0,
+    (S_GETREG_B32 -26595), sub0,
     (S_MOV_B32 (i32 0)), sub1)
 >;
 } // let OtherPredicates = [HasNoSMemTimeInst]



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