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[AMD Official Use Only - Internal Distribution Only]<br>
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<p class="MsoNormal">I need to figure it out. It is tablegen produced some C++ code, which in turn resulted in UB. At the moment I have just put the constant there to clear the testing, the actual expected behavior is still questionable. It was !shl($var, 11)
and the $var was negative. So it is a shift of a negative value. I do not see any issue with the shl of a negative value in 2-complement off hand given the size is the same size.<o:p></o:p></p>
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<p class="MsoNormal">Stas<o:p></o:p></p>
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<p class="MsoNormal"><b>From:</b> Arsenault, Matthew <Matthew.Arsenault@amd.com> <br>
<b>Sent:</b> Monday, June 15, 2020 17:28<br>
<b>To:</b> llvm-commits@lists.llvm.org; Mekhanoshin, Stanislav <Stanislav.Mekhanoshin@amd.com>; Stanislav Mekhanoshin <llvmlistbot@llvm.org><br>
<b>Subject:</b> Re: [llvm] 576fa5a - [AMDGPU] make ubsan happy with unsigned left shift<o:p></o:p></p>
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<p style="margin:15.0pt"><span style="font-size:10.0pt;font-family:"Arial",sans-serif;color:#0078D7">[AMD Official Use Only - Internal Distribution Only]<o:p></o:p></span></p>
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<p class="MsoNormal"><span style="font-size:12.0pt;color:black">This was in the tabelgen shift? Tablegen should be fixed instead?<o:p></o:p></span></p>
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<p class="MsoNormal"><b><span style="color:black">From:</span></b><span style="color:black"> llvm-commits <<a href="mailto:llvm-commits-bounces@lists.llvm.org">llvm-commits-bounces@lists.llvm.org</a>> on behalf of Stanislav Mekhanoshin via llvm-commits <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>><br>
<b>Sent:</b> Monday, June 15, 2020 5:21 PM<br>
<b>To:</b> <a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a> <<a href="mailto:llvm-commits@lists.llvm.org">llvm-commits@lists.llvm.org</a>><br>
<b>Subject:</b> [llvm] 576fa5a - [AMDGPU] make ubsan happy with unsigned left shift</span>
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Author: Stanislav Mekhanoshin<br>
Date: 2020-06-15T17:21:10-07:00<br>
New Revision: 576fa5a50c8509977835031d190f8906e1dbb075<br>
<br>
URL: <a href="https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fllvm%2Fllvm-project%2Fcommit%2F576fa5a50c8509977835031d190f8906e1dbb075&data=02%7C01%7CMatthew.Arsenault%40amd.com%7C8347580ea9c14e02566d08d8118b3468%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637278636882998969&sdata=03WSLSu42FOTqFmGc%2FedlUjWr5X0QmQdPOb%2FDkmrULk%3D&reserved=0">
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<br>
LOG: [AMDGPU] make ubsan happy with unsigned left shift<br>
<br>
Fixes UBSAN error after rG9ee272f13d88f090817235ef4f91e56bb2a153d6<br>
A trivial signed/unsigned shift.<br>
<br>
Added:<br>
<br>
<br>
Modified:<br>
llvm/lib/Target/AMDGPU/SMInstructions.td<br>
<br>
Removed:<br>
<br>
<br>
<br>
################################################################################<br>
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td<br>
index 252f191a2f66..df21c864ccad 100644<br>
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td<br>
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td<br>
@@ -860,7 +860,7 @@ let OtherPredicates = [HasNoSMemTimeInst] in {<br>
def : GCNPat <<br>
(i64 (readcyclecounter)),<br>
(REG_SEQUENCE SReg_64,<br>
- (S_GETREG_B32 getHwRegImm<HWREG.SHADER_CYCLES, 0, -12>.ret), sub0,<br>
+ (S_GETREG_B32 -26595), sub0,<br>
(S_MOV_B32 (i32 0)), sub1)<br>
>;<br>
} // let OtherPredicates = [HasNoSMemTimeInst]<br>
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