[PATCH] D81506: [X86] Automatically harden inline assembly RET instructions against Load Value Injection (LVI)
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 9 14:54:54 PDT 2020
craig.topper added inline comments.
================
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3216
emitWarningForSpecialLVIInstruction(Inst.getLoc());
+ Out.emitInstruction(Inst, getSTI());
return true;
----------------
Why did emitInstruction have to get repeated everywhere? Aren't we still emitting the original ret from the user after the mitigation? So its not any different than inserting an LFENCE. Am I missing something?
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D81506/new/
https://reviews.llvm.org/D81506
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