[PATCH] D81383: [VE] Support lowering to NND instruction

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 created this revision.
kaz7 added reviewers: simoll, k-ishizaka.
kaz7 added projects: LLVM, VE.
Herald added subscribers: llvm-commits, hiraditya.
simoll added a comment.

Just one nit.



================
Comment at: llvm/lib/Target/VE/VEISelLowering.cpp:541-547
+  // VE allows different immediate values for X and Y where ~X & Y.
+  // Only simm7 works for X, and only mimm works for Y.  It doesn't match
+  // hasAndNot requirements, so return false for all immediate values now.
+  // FIXME: Change hasAndNot function to have two operands to work it
+  //        correctly with Aurora VE.
+  if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Y))
+    return false;
----------------
Why not `return true` for all scalar NANDs? Constants can always be pulled through registers if we cannot turn them into immediates.


Support NND instruction of Aurora VE.  Add hasAndNot function also
for optimization.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81383

Files:
  llvm/lib/Target/VE/VEISelLowering.cpp
  llvm/lib/Target/VE/VEISelLowering.h
  llvm/lib/Target/VE/VEInstrInfo.td
  llvm/test/CodeGen/VE/cttz.ll
  llvm/test/CodeGen/VE/nnd.ll

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