[PATCH] D81172: [AMDGPU] Implement hardware bug workaround for image instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

Also needs to update the GlobalISel path



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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:5370-5371
+      // instructions.
+      if (IsD16 && !Subtarget->hasUnpackedD16VMem() &&
+          !(BaseOpcode->Gather4 && Subtarget->hasImageGather4D16Bug()))
         NumVDataDwords = (DMaskLanes + 1) / 2;
----------------
IsD16 && (!hasUnpackedD16() || (Gather4 && hasGatherbug))?


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:6700
+    // Group pairs of i16 into v2i16 and bitcast to i32
+    SmallVector<SDValue, 4> PackedElts;
+    EVT Vec2VT = EVT::getVectorVT(*DAG.getContext(), MVT::i16, 2);
----------------
You can initialize this to the target size and then avoid push_back


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:6701
+    SmallVector<SDValue, 4> PackedElts;
+    EVT Vec2VT = EVT::getVectorVT(*DAG.getContext(), MVT::i16, 2);
+    for (unsigned i = 0 ; i < Elts.size() / 2 ; i += 1)
----------------
This is the same as just MVT::v2i16


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:6703
+    for (unsigned i = 0 ; i < Elts.size() / 2 ; i += 1)
+    {
+      SDValue Pair = DAG.getBuildVector(Vec2VT, DL, {Elts[i * 2],
----------------
Formatting


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D81172/new/

https://reviews.llvm.org/D81172