[PATCH] D81108: [AArch64] Fix ldst-opt of multiple disjunct subregs.

[Florian Hahn via Phabricator via llvm-commits]

fhahn created this revision.
fhahn added reviewers: efriedma, dmgreen, paquette, t.p.northover.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.

Currently aarch64-ldst-opt will incorrectly rename registers with
multiple disjunct subregisters (e.g. result of LD3). This patch updates
the canRenameUpToDef to bail out if it encounters such a register class
that contains the register to rename.

Fixes PR46105.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81108

Files:
  llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
  llvm/test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir


Index: llvm/test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir
===================================================================
--- llvm/test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir
+++ llvm/test/CodeGen/AArch64/stp-opt-with-renaming-ld3.mir
@@ -1,4 +1,4 @@
-# RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -aarch64-load-store-renaming=true -o - %s | FileCheck %s
+# RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -aarch64-load-store-renaming=true -o - -verify-machineinstrs %s | FileCheck %s
 --- |
   define void @test_ld3(<8 x i8>* %a1) {
   entry:
@@ -10,11 +10,12 @@
 ---
 # CHECK-LABEL: name: test_ld3
 # CHECK: bb.0.entry:
-# CHECK:       renamable $x0, $d1_d2_d3 = LD3Threev8b_POST killed renamable $x0, $xzr
+# CHECK:       renamable $x0, renamable $d0_d1_d2 = LD3Threev8b_POST killed renamable $x0, $xzr
 # CHECK-NEXT:  STPDi renamable $d0, renamable $d1, $fp, -6 :: (store 8)
+# CHECK-NEXT:  STURDi renamable $d2, $fp, -32, implicit killed $d0_d1_d2 :: (store 8 into %ir.s1)
 # CHECK-NEXT:  renamable $d0_d1_d2 = LD3Threev8b killed renamable $x0 :: (load 24 from %ir.a1, align 32)
-# CHECK-NEXT:  STPDi $d3, renamable $d0, $fp, -4 :: (store 8 into %ir.s1), (store 8)
-# CHECK-NEXT:  STPDi renamable $d1, renamable $d2, $fp, -2 :: (store 8)
+# CHECK-NEXT:  STPDi renamable $d0, renamable $d1, $fp, -3 :: (store 8)
+# CHECK-NEXT:  STURDi renamable $d2, $fp, -8, implicit killed $d0_d1_d2 :: (store 8)
 # CHECK-NEXT:  RET undef $lr
 #
 name:            test_ld3
Index: llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -1287,7 +1287,20 @@
     LLVM_DEBUG(dbgs() << "  Operand not killed at " << FirstMI << "\n");
     return false;
   }
-  auto canRenameMOP = [](const MachineOperand &MOP) {
+  auto canRenameMOP = [TRI](const MachineOperand &MOP) {
+    if (MOP.isReg()) {
+      auto *RegClass = TRI->getMinimalPhysRegClass(MOP.getReg());
+      // Renaming registers with multiple disjunct sub-registers (e.g. the
+      // result of a LD3) means that all sub-registers are renamed, potentially
+      // impacting other instructions we did not check. Bail out.
+      if (RegClass->HasDisjunctSubRegs) {
+        LLVM_DEBUG(
+            dbgs()
+            << "  Cannot rename operands with multiple disjunct subregisters ("
+            << MOP << ")\n");
+        return false;
+      }
+    }
     return MOP.isImplicit() ||
            (MOP.isRenamable() && !MOP.isEarlyClobber() && !MOP.isTied());
   };


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