[PATCH] D81082: [PowerPC] Do not add the relocation addend to the instruction encoding

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp created this revision.
stefanp added reviewers: nemanjai, lei, sfertile, PowerPC, hfinkel.
Herald added subscribers: shchenz, kbarton, hiraditya.
Herald added a project: LLVM.

We should not be adding the relocation addend to the instruction encoding.
This patch removes that and sets those bits to zero.


https://reviews.llvm.org/D81082

Files:
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
  llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll


Index: llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll
+++ llvm/test/CodeGen/PowerPC/pcrel-relocation-plus-offset.ll
@@ -16,7 +16,7 @@
 ; CHECK-S-NEXT:    plwa r3, array2 at PCREL+28(0), 1
 ; CHECK-S-NEXT:    blr
 ; CHECK-O-LABEL: <getElementLocal7>:
-; CHECK-O:         00 00 10 04 1c 00 60 a4       plwa 3, 28(0), 1
+; CHECK-O:         00 00 10 04 00 00 60 a4       plwa 3, 0(0), 1
 ; CHECK-O-NEXT:    0000000000000000:  R_PPC64_PCREL34      array2+0x1c
 ; CHECK-O-NEXT:    20 00 80 4e                   blr
 entry:
@@ -30,7 +30,7 @@
 ; CHECK-S-NEXT:    plwa r3, array2 at PCREL-8(0), 1
 ; CHECK-S-NEXT:    blr
 ; CHECK-O-LABEL: <getElementLocalNegative>:
-; CHECK-O:         ff ff 13 04 f8 ff 60 a4       plwa 3, -8(0), 1
+; CHECK-O:         00 00 10 04 00 00 60 a4       plwa 3, 0(0), 1
 ; CHECK-O-NEXT:    0000000000000020:  R_PPC64_PCREL34      array2-0x8
 ; CHECK-O-NEXT:    20 00 80 4e                   blr
 entry:
Index: llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
===================================================================
--- llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
+++ llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
@@ -219,8 +219,7 @@
     Fixups.push_back(
         MCFixup::create(0, Expr,
                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
-    // There is no offset to return so just return 0.
-    return 0;
+    break;
   }
   case MCExpr::Binary: {
     // Relocation plus some offset.
@@ -242,6 +241,7 @@
     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(LHS);
     (void)SRE;
     const MCConstantExpr *CE = cast<MCConstantExpr>(RHS);
+    assert(isInt<34>(CE->getValue()) && "Value must fit in 34 bits.");
 
     // Currently these are the only valid PCRelative Relocations.
     assert((SRE->getKind() == MCSymbolRefExpr::VK_PCREL ||
@@ -251,11 +251,10 @@
     Fixups.push_back(
         MCFixup::create(0, Expr,
                         static_cast<MCFixupKind>(PPC::fixup_ppc_pcrel34)));
-    assert(isInt<34>(CE->getValue()) && "Value must fit in 34 bits.");
-    // Return the offset that should be added to the relocation by the linker.
-    return (CE->getValue() & 0x3FFFFFFFFUL) | RegBits;
-    }
+    break;
+  }
   }
+  return 0;
 }
 
 uint64_t


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