[PATCH] D81006: [PowerPC] fix a bug for folding RLWINM(LI) to LI due to wrap mask

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: hfinkel, PowerPC, steven.zhang.
Herald added subscribers: llvm-commits, wuzish, kbarton, hiraditya, nemanjai.
Herald added a project: LLVM.

This is found during code review for https://reviews.llvm.org/D80907

See comment https://reviews.llvm.org/D80907#2068594

Peephole pass will convert following pattern:

  %1:gprc = LI 100
  %2:gprc = RLWINM %1:gprc, 1, 3, 2

to

  %2:gprc = LI 0

The wrap mask is not handled well in `convertToImmediateForm`


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D81006

Files:
  llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
  llvm/test/CodeGen/PowerPC/fold-rlwinm.mir


Index: llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
===================================================================
--- llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
+++ llvm/test/CodeGen/PowerPC/fold-rlwinm.mir
@@ -1,5 +1,7 @@
 # RUN: llc -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu \
 # RUN:   -run-pass ppc-mi-peepholes %s -o - -verify-machineinstrs | FileCheck %s
+# RUN: llc -ppc-asm-full-reg-names -mtriple=powerpc64le-unknown-linux-gnu -ppc-convert-rr-to-ri \
+# RUN:   -run-pass ppc-mi-peepholes %s -o - -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-IMM
 
 ---
 name: testFoldRLWINM
@@ -168,3 +170,17 @@
     ; CHECK: %3:gprc = RLWINM %2, 19, 10, 20
     BLR8 implicit $lr8, implicit $rm
 ...
+---
+name: testFoldRLWINMLIWrapMask
+#CHECK: name: testFoldRLWINMLIWrapMask
+tracksRegLiveness: true
+body: |
+  bb.0.entry:
+    liveins: $x3 
+    %0:gprc = COPY $x3 
+    %1:gprc = LI 100
+    ; CHECK-IMM: %2:gprc = LI 200
+    %2:gprc = RLWINM %1:gprc, 1, 3, 2
+    STW %2:gprc, %0:gprc, 100
+    BLR8 implicit $lr8, implicit $rm 
+...
Index: llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ llvm/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -3417,8 +3417,12 @@
     int64_t ME = MI.getOperand(4).getImm();
     APInt InVal(32, SExtImm, true);
     InVal = InVal.rotl(SH);
-    // Set the bits (        MB + 32        ) to (        ME + 32        ).
-    uint64_t Mask = ((1LLU << (32 - MB)) - 1) & ~((1LLU << (31 - ME)) - 1);
+    APInt Mask = APInt::getBitsSetWithWrap(32, 32 - ME - 1, 32 - MB);
+    // Current APInt::getBitsSetWithWrap sets all bits to 0 if loBit is equal
+    // to highBit.
+    // If MB - ME == 1, we expect a full set mask instead of 0.
+    if (MB - ME == 1)
+      Mask.setAllBits();
     InVal &= Mask;
     // Can't replace negative values with an LI as that will sign-extend
     // and not clear the left bits. If we're setting the CR bit, we will use


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