[PATCH] D80920: AMDGPU: Fix alignment for dynamic allocas

[Madhur Amilkanthwar via Phabricator via llvm-commits]

madhur13490 added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll:98
 ; GCN-NEXT:    s_add_i32 s6, s32, 0x1000
-; GCN-NEXT:    s_andn2_b32 s6, s6, 63
+; GCN-NEXT:    s_and_b32 s6, s6, 0xfffff000
 ; GCN-NEXT:    s_lshl_b32 s7, s7, 2
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Why is the opcode changed in assembly? you seemed to keep same DAG Opcode.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D80920/new/

https://reviews.llvm.org/D80920