[PATCH] D80920: AMDGPU: Fix alignment for dynamic allocas

[Matt Arsenault via Phabricator via llvm-commits]

arsenm created this revision.
arsenm added reviewers: scott.linder, rampitec.
Herald added subscribers: kerbowa, hiraditya, t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, jvesely, kzhuravl.
Herald added a project: LLVM.

The alignment value also needs to be scaled by the wave size.


https://reviews.llvm.org/D80920

Files:
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll


Index: llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
+++ llvm/test/CodeGen/AMDGPU/non-entry-alloca.ll
@@ -95,7 +95,7 @@
 ; GCN-NEXT:    s_cbranch_scc1 BB1_2
 ; GCN-NEXT:  ; %bb.1: ; %bb.0
 ; GCN-NEXT:    s_add_i32 s6, s32, 0x1000
-; GCN-NEXT:    s_andn2_b32 s6, s6, 63
+; GCN-NEXT:    s_and_b32 s6, s6, 0xfffff000
 ; GCN-NEXT:    s_lshl_b32 s7, s7, 2
 ; GCN-NEXT:    s_mov_b32 s32, s6
 ; GCN-NEXT:    v_mov_b32_e32 v2, s6
@@ -223,7 +223,7 @@
 ; GCN-NEXT:    s_cbranch_execz BB3_2
 ; GCN-NEXT:  ; %bb.1: ; %bb.0
 ; GCN-NEXT:    s_add_i32 s6, s32, 0x1000
-; GCN-NEXT:    s_andn2_b32 s6, s6, 63
+; GCN-NEXT:    s_and_b32 s6, s6, 0xfffff000
 ; GCN-NEXT:    v_mov_b32_e32 v2, 0
 ; GCN-NEXT:    v_mov_b32_e32 v5, s6
 ; GCN-NEXT:    v_mov_b32_e32 v6, 1
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -3126,9 +3126,13 @@
 
   unsigned StackAlign = TFL->getStackAlignment();
   Tmp1 = DAG.getNode(Opc, dl, VT, SP, ScaledSize); // Value
-  if (Align > StackAlign)
-    Tmp1 = DAG.getNode(ISD::AND, dl, VT, Tmp1,
-                       DAG.getConstant(-(uint64_t)Align, dl, VT));
+  if (Align > StackAlign) {
+    Tmp1 = DAG.getNode(
+      ISD::AND, dl, VT, Tmp1,
+      DAG.getConstant(-(uint64_t)Align << ST.getWavefrontSizeLog2(), dl, VT));
+  }
+
+
   Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1);    // Output chain
   Tmp2 = DAG.getCALLSEQ_END(
       Chain, DAG.getIntPtrConstant(0, dl, true),


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