[PATCH] D80158: [AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO.

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir:5
+# GCN: %{{[0-9]+}}:vgpr_32, %[[CO1:[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 killed %{{[0-9]+}}, %{{[0-9]+}}, 0, implicit $exec
+# GCN: %{{[0-9]+}}:vgpr_32, %[[CO2:[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 killed %{{[0-9]+}}, %{{[0-9]+}}, %[[CO1]], 0, implicit $exec
+# GCN: %{{[0-9]+}}:vgpr_32, %{{[0-9]+}}:sreg_64_xexec = V_ADDC_U32_e64 %{{[0-9]+}}, killed %{{[0-9]+}}, %[[CO2]], 0, implicit $exec
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Doesn't test for the copy? I would also probably just use update_mir_test_checks here


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Comment at: llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir:8
+
+name:            floatlibfunc
+tracksRegLiveness: true
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Better test name?


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Comment at: llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir:10
+tracksRegLiveness: true
+registers:
+
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Should be able to drop the register section


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D80158/new/

https://reviews.llvm.org/D80158