[PATCH] D80158: [AMDGPU] Fix for the lost CarryOut/CarryIn register operands in S_ADD/SUB_CO_PSEUDO.
Alexander via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed May 20 17:41:57 PDT 2020
alex-t updated this revision to Diff 265395.
alex-t added a comment.
Explicit register class comparison changed to constrain reg class. Test added.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D80158/new/
https://reviews.llvm.org/D80158
Files:
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
Index: llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AMDGPU/s_add_co_pseudo_lowering.mir
@@ -0,0 +1,55 @@
+# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-fix-sgpr-copies %s -o - | FileCheck -check-prefix=GCN %s
+---
+# GCN-LABEL: bb.0:
+# GCN: %{{[0-9]+}}:vgpr_32, %[[CO1:[0-9]+]]:sreg_64_xexec = V_ADD_I32_e64 killed %{{[0-9]+}}, %{{[0-9]+}}, 0, implicit $exec
+# GCN: %{{[0-9]+}}:vgpr_32, %[[CO2:[0-9]+]]:sreg_64_xexec = V_ADDC_U32_e64 killed %{{[0-9]+}}, %{{[0-9]+}}, %[[CO1]], 0, implicit $exec
+# GCN: %{{[0-9]+}}:vgpr_32, %{{[0-9]+}}:sreg_64_xexec = V_ADDC_U32_e64 %{{[0-9]+}}, killed %{{[0-9]+}}, %[[CO2]], 0, implicit $exec
+
+name: floatlibfunc
+tracksRegLiveness: true
+registers:
+
+ - { id: 0, class: vgpr_32, preferred-register: '' }
+ - { id: 1, class: vgpr_32, preferred-register: '' }
+ - { id: 2, class: vgpr_32, preferred-register: '' }
+ - { id: 3, class: sreg_32, preferred-register: '' }
+ - { id: 4, class: sreg_32, preferred-register: '' }
+ - { id: 5, class: sreg_32, preferred-register: '' }
+ - { id: 6, class: sreg_32, preferred-register: '' }
+ - { id: 7, class: sreg_32, preferred-register: '' }
+ - { id: 8, class: sreg_32, preferred-register: '' }
+ - { id: 9, class: vgpr_32, preferred-register: '' }
+ - { id: 10, class: sreg_64_xexec, preferred-register: '' }
+ - { id: 11, class: sreg_32, preferred-register: '' }
+ - { id: 12, class: sreg_32, preferred-register: '' }
+ - { id: 13, class: sreg_64_xexec, preferred-register: '' }
+ - { id: 14, class: sreg_32, preferred-register: '' }
+ - { id: 15, class: sreg_32, preferred-register: '' }
+ - { id: 16, class: sreg_32, preferred-register: '' }
+ - { id: 17, class: sreg_32, preferred-register: '' }
+ - { id: 18, class: sreg_64_xexec, preferred-register: '' }
+ - { id: 19, class: sreg_32, preferred-register: '' }
+
+body: |
+
+ bb.0:
+ liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr0, $sgpr1, $sgpr2
+ %0:vgpr_32 = COPY $vgpr0
+ %6:sreg_32 = COPY %0
+ %1:vgpr_32 = COPY $vgpr1
+ %2:vgpr_32 = COPY $vgpr2
+ %3:sreg_32 = COPY $sgpr0
+ %4:sreg_32 = COPY $sgpr1
+ %5:sreg_32 = COPY $sgpr2
+ %20:vgpr_32 = COPY %3
+ %7:sreg_32 = S_MUL_I32 %6, %4
+ %9:vgpr_32, %10:sreg_64_xexec = V_ADD_I32_e64 killed %7, %20, 0, implicit $exec
+ %8:sreg_32 = S_MUL_HI_U32 %4, %5
+ %11:sreg_32 = S_MOV_B32 -614296167
+ %12:sreg_32 = S_MUL_I32 %6, %3
+ %14:sreg_32, %13:sreg_64_xexec = S_ADD_CO_PSEUDO killed %12, killed %11, killed %10, implicit-def dead $scc
+ %15:sreg_32 = S_MUL_HI_U32 %4, %14
+ %16:sreg_32 = S_MOV_B32 -181084736
+ %17:sreg_32 = S_MUL_I32 %15, %16
+ %19:sreg_32, %18:sreg_64_xexec = S_ADD_CO_PSEUDO killed %16, killed %17, killed %13, implicit-def dead $scc
+...
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -5177,18 +5177,24 @@
? AMDGPU::V_ADDC_U32_e64
: AMDGPU::V_SUBB_U32_e64;
const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
- Register DummyCReg = MRI.createVirtualRegister(CarryRC);
- Register CarryReg = MRI.createVirtualRegister(CarryRC);
+
+ Register CarryInReg = Inst.getOperand(4).getReg();
+ if (!MRI.constrainRegClass(CarryInReg, CarryRC)) {
+ Register NewCarryReg = MRI.createVirtualRegister(CarryRC);
+ BuildMI(*MBB, &Inst, Inst.getDebugLoc(), get(AMDGPU::COPY), NewCarryReg)
+ .addReg(CarryInReg);
+ }
+
+ Register CarryOutReg = Inst.getOperand(1).getReg();
+
Register DestReg = MRI.createVirtualRegister(RI.getEquivalentVGPRClass(
MRI.getRegClass(Inst.getOperand(0).getReg())));
- BuildMI(*MBB, &Inst, Inst.getDebugLoc(), get(AMDGPU::COPY), CarryReg)
- .addReg(Inst.getOperand(4).getReg());
MachineInstr *CarryOp =
BuildMI(*MBB, &Inst, Inst.getDebugLoc(), get(Opc), DestReg)
- .addReg(DummyCReg, RegState::Define | RegState::Dead)
+ .addReg(CarryOutReg, RegState::Define)
.add(Inst.getOperand(2))
.add(Inst.getOperand(3))
- .addReg(CarryReg, RegState::Kill)
+ .addReg(CarryInReg)
.addImm(0);
legalizeOperands(*CarryOp);
MRI.replaceRegWith(Inst.getOperand(0).getReg(), DestReg);
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