[PATCH] D75988: [AArch64][SVE] Add support for spilling/filling ZPR2/3/4

[Cullen Rhodes via Phabricator via llvm-commits]

c-rhodes updated this revision to Diff 264202.
c-rhodes edited the summary of this revision.
c-rhodes added a comment.

Use `getSpillSize` switch in `storeRegToStackSlot`/`loadRegFromStackSlot` for SVE predicate and vector registers.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75988/new/

https://reviews.llvm.org/D75988

Files:
  llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/test/CodeGen/AArch64/spillfill-sve.mir

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