[PATCH] D79776: [AMDGPU] Allow use of StackPtrOffsetReg when building spills

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll:65
 
+attributes #0 = { "amdgpu-num-sgpr"="30" }
 attributes #1 = { nounwind readnone }
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critson wrote:
> arsenm wrote:
> > Can you use amdgpu-max-waves-per-eu? I'm trying to move away from the direct register limit attributes
> Unfortunately amdgpu-waves-per-eu does not allow us to constrain the SGPRs low enough to trigger the bug without making the test much bigger.
Don't you just need a big block of sgpr use asm to cover the difference?


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  https://reviews.llvm.org/D79776/new/

https://reviews.llvm.org/D79776