[PATCH] D79705: [TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator

[Victor Campos via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGcac6a26f3813: [TableGen] Fix register class handling in TableGen's DAG ISel Matcher Generator (authored by vhscampos).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79705/new/

https://reviews.llvm.org/D79705

Files:
  llvm/test/TableGen/dag-isel-regclass-emit-enum.td
  llvm/utils/TableGen/DAGISelMatcherGen.cpp


Index: llvm/utils/TableGen/DAGISelMatcherGen.cpp
===================================================================
--- llvm/utils/TableGen/DAGISelMatcherGen.cpp
+++ llvm/utils/TableGen/DAGISelMatcherGen.cpp
@@ -707,9 +707,19 @@
     if (Def->isSubClassOf("RegisterOperand"))
       Def = Def->getValueAsDef("RegClass");
     if (Def->isSubClassOf("RegisterClass")) {
-      std::string Value = getQualifiedName(Def) + "RegClassID";
-      AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
-      ResultOps.push_back(NextRecordedOperandNo++);
+      // If the register class has an enum integer value greater than 127, the
+      // encoding overflows the limit of 7 bits, which precludes the use of
+      // StringIntegerMatcher. In this case, fallback to using IntegerMatcher.
+      const CodeGenRegisterClass &RC =
+          CGP.getTargetInfo().getRegisterClass(Def);
+      if (RC.EnumValue <= 127) {
+        std::string Value = getQualifiedName(Def) + "RegClassID";
+        AddMatcher(new EmitStringIntegerMatcher(Value, MVT::i32));
+        ResultOps.push_back(NextRecordedOperandNo++);
+      } else {
+        AddMatcher(new EmitIntegerMatcher(RC.EnumValue, MVT::i32));
+        ResultOps.push_back(NextRecordedOperandNo++);
+      }
       return;
     }
 
Index: llvm/test/TableGen/dag-isel-regclass-emit-enum.td
===================================================================
--- /dev/null
+++ llvm/test/TableGen/dag-isel-regclass-emit-enum.td
@@ -0,0 +1,39 @@
+// RUN: llvm-tblgen -gen-dag-isel -I %p/../../include %s | FileCheck %s
+
+include "llvm/Target/Target.td"
+
+def TestTargetInstrInfo : InstrInfo;
+
+def TestTarget : Target {
+  let InstructionSet = TestTargetInstrInfo;
+}
+
+let Namespace = "TestNamespace" in {
+
+def R0 : Register<"r0">;
+
+foreach i = 0-127 in {
+def GPR#i : RegisterClass<"TestTarget", [i32], 32,
+                          (add R0)>;
+}
+
+def GPRAbove127 : RegisterClass<"TestTarget", [i32], 32,
+                                (add R0)>;
+} // end Namespace TestNamespace
+
+// CHECK:      OPC_CheckOpcode, TARGET_VAL(ISD::ADD),
+// CHECK-NEXT: OPC_RecordChild0, // #0 = $src
+// CHECK-NEXT: OPC_Scope, 14, /*->20*/ // 2 children in Scope
+// CHECK-NEXT: OPC_CheckChild1Integer, 0,
+// CHECK-NEXT: OPC_EmitInteger, MVT::i32, 0|128,1/*128*/,
+// CHECK-NEXT: OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+// CHECK-NEXT:     MVT::i32, 2/*#Ops*/, 1, 0,
+def : Pat<(i32 (add i32:$src, (i32 0))),
+          (COPY_TO_REGCLASS GPRAbove127, GPR0:$src)>;
+
+// CHECK:      OPC_CheckChild1Integer, 1,
+// CHECK-NEXT: OPC_EmitInteger, MVT::i32, TestNamespace::GPR127RegClassID,
+// CHECK-NEXT: OPC_MorphNodeTo1, TARGET_VAL(TargetOpcode::COPY_TO_REGCLASS), 0,
+// CHECK-NEXT:     MVT::i32, 2/*#Ops*/, 1, 0,
+def : Pat<(i32 (add i32:$src, (i32 1))),
+          (COPY_TO_REGCLASS GPR127, GPR0:$src)>;


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