[PATCH] D79768: [ARM] Exclude LR from register classes in low overhead loops

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> Architecturally the loop info is created when you execute an LE and cleared when you otherwise write to LR.

Oh, hmm.  Maybe we do need something drastic, then.  I'm a little worried about cases where it isn't profitable to emit a low-overhead loop due to the increased register pressure, but maybe you can control that with other heuristics.

> Are you worried about more than the 4 + 2 extra that are here? This, with an assert in the NDEBUG block, managed to pass all the benchmarks I threw it at plus all the llvm tests. Do you worry it will need a lot of others?

It's not really the raw number I'm concerned about; more that it's hard to enumerate them, and anyone adding a new register class likely won't be aware of the need to update this code.  Also, some register classes only show up in obscure circumstances.  For example, hGPR only shows up with inline asm, and GPRwithAPSR_NZCVnosp only shows up with CDE.

On a side-note, you probably want to be careful about restricting register classes if inline asm is involved; you might force the allocator to run out of registers.


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https://reviews.llvm.org/D79768