[PATCH] D79768: [ARM] Exclude LR from register classes in low overhead loops

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 263524.
dmgreen added a comment.

Added GPRwithZR and GPRwithZRnosp


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79768/new/

https://reviews.llvm.org/D79768

Files:
  llvm/lib/Target/ARM/ARM.h
  llvm/lib/Target/ARM/ARMRegisterInfo.td
  llvm/lib/Target/ARM/ARMRegisterTypePass.cpp
  llvm/lib/Target/ARM/ARMTargetMachine.cpp
  llvm/lib/Target/ARM/CMakeLists.txt
  llvm/test/CodeGen/ARM/O3-pipeline.ll
  llvm/test/CodeGen/Thumb2/LowOverheadLoops/regalloc.ll
  llvm/test/CodeGen/Thumb2/high-reg-spill.mir
  llvm/test/CodeGen/Thumb2/mve-gather-increment.ll
  llvm/test/CodeGen/Thumb2/mve-postinc-lsr.ll
  llvm/test/CodeGen/Thumb2/mve-satmul-loops.ll

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