[llvm] adf3b8e - [X86] Add assembler support for {vex} prefix to match GNU as.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-05-08T11:50:58-07:00
New Revision: adf3b8e366160aaf7f6a55ecec8f5d0342a40dd3

URL: https://github.com/llvm/llvm-project/commit/adf3b8e366160aaf7f6a55ecec8f5d0342a40dd3
DIFF: https://github.com/llvm/llvm-project/commit/adf3b8e366160aaf7f6a55ecec8f5d0342a40dd3.diff

LOG: [X86] Add assembler support for {vex} prefix to match GNU as.

This does the same thing as {vex2}. Which is give an error
if the instruction can't be done with VEX. It doesn't force
the instruction to use 2 byte VEX. That's already the preference
if its possible. Therefore {vex} is a clearer name.

Added: 
    

Modified: 
    llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
    llvm/test/MC/X86/x86_errors.s

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
index b68206de7ff4..ee76fe9fe32f 100644
--- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
+++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp
@@ -74,7 +74,7 @@ class X86AsmParser : public MCTargetAsmParser {
 
   enum VEXEncoding {
     VEXEncoding_Default,
-    VEXEncoding_VEX2,
+    VEXEncoding_VEX,
     VEXEncoding_VEX3,
     VEXEncoding_EVEX,
   };
@@ -2473,8 +2473,8 @@ bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
         return Error(Parser.getTok().getLoc(), "Expected '}'");
       Parser.Lex(); // Eat curly.
 
-      if (Prefix == "vex2")
-        ForcedVEXEncoding = VEXEncoding_VEX2;
+      if (Prefix == "vex" || Prefix == "vex2")
+        ForcedVEXEncoding = VEXEncoding_VEX;
       else if (Prefix == "vex3")
         ForcedVEXEncoding = VEXEncoding_VEX3;
       else if (Prefix == "evex")
@@ -3223,7 +3223,7 @@ unsigned X86AsmParser::checkTargetMatchPredicate(MCInst &Inst) {
       (MCID.TSFlags & X86II::EncodingMask) != X86II::EVEX)
     return Match_Unsupported;
 
-  if ((ForcedVEXEncoding == VEXEncoding_VEX2 ||
+  if ((ForcedVEXEncoding == VEXEncoding_VEX ||
        ForcedVEXEncoding == VEXEncoding_VEX3) &&
       (MCID.TSFlags & X86II::EncodingMask) != X86II::VEX)
     return Match_Unsupported;

diff  --git a/llvm/test/MC/X86/x86_errors.s b/llvm/test/MC/X86/x86_errors.s
index f9cdc150b667..e0a971f18e52 100644
--- a/llvm/test/MC/X86/x86_errors.s
+++ b/llvm/test/MC/X86/x86_errors.s
@@ -168,6 +168,10 @@ cltq
 // 32: error: instruction requires: 64-bit mode
 cmpxchg16b (%eax)
 
+// 32: error: unsupported instruction
+// 64: error: unsupported instruction
+{vex} vmovdqu32 %xmm0, %xmm0
+
 // 32: error: unsupported instruction
 // 64: error: unsupported instruction
 {vex2} vmovdqu32 %xmm0, %xmm0