[PATCH] D79606: [ARM] Convert VDUPLANE to VDUP under MVE

[Dave Green via Phabricator via llvm-commits]

dmgreen marked an inline comment as done.
dmgreen added a comment.

In D79606#2026276 <https://reviews.llvm.org/D79606#2026276>, @efriedma wrote:

> If you never want VDUPLANE, it doesn't seem like there's much point to generating it in the first place; I guess you want to continue supporting it just to make it easier to share code between NEON and MVE?


Yep. They can be generate in a few different place, and although it would be possible to stop them being created, it complicates the logic. I agree it's strange on it's own to create a node only to convert it into something else, but if it keeps the buildvector/vectorshuffle code simpler and helps them be shared between neon and mve, I think this is probably simpler overall.



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Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:13853
+    SDValue Extract;
+    if (ExtractVT == MVT::f16) {
+      // FP16 are always a little special and go via a VGETLANEu to stop it
----------------
efriedma wrote:
> I guess if you didn't have a special case for f16 here, you could still eventually get to the same place, but it would take some extra steps?
I was originally thinking this would need to look at the demanded bits of the VMOVrh which complicate things, but yeah it's simpler than that. With VGETLANEu we can add a fold easily enough and still get the top lanes correct. I can change things around to do it that way.


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