[PATCH] D78129: Add Marvell ThunderX3T110 support

[Wei Zhao via Phabricator via llvm-commits]

wxz2020 marked an inline comment as done.
wxz2020 added a comment.

I tried to set CompleteModel = 0 on line 25 in file llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td

The same error is still there.



================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:849-857
+// These pointer authentication instructions require armv8.3a
+let Predicates = [HasV8_3a, HasPA] in {
 let Uses = [LR], Defs = [LR] in {
   def PACIAZ   : SystemNoOperands<0b000, "hint\t#24">;
   def PACIBZ   : SystemNoOperands<0b010, "hint\t#26">;
   let isAuthenticated = 1 in {
     def AUTIAZ   : SystemNoOperands<0b100, "hint\t#28">;
----------------
wxz2020 wrote:
> chill wrote:
> > wxz2020 wrote:
> > > wxz2020 wrote:
> > > > ktkachov wrote:
> > > > > IIRC these instructions are deliberately allowed in pre-armv8.3 targets because they are encoded in the NOP-space and can be deployed on pre-armv8.3 targets 
> > > > I will do some research on this.
> > > According to the documents, pointer authenticatoin got officially supporoted starting from armv8.3.  
> > These instructions are executed as NOP on pre v8.3-A architectures. It allows you to have a single compatible binary that works correctly on pre v8.3-a (ofc, without pointer authentication), as well as on
> > 8.3-a and later cores, with pointer authentication.
> > 
> > Please, remove the predicates.
> Agree. Will remove it.
One questions here, we want to model these instructions in our machine model, scroll down to line 1992-1997, in
llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td below.

However, if we remove this predicate here, tblgen will complain the following errors for all the instructions defined in line 1992-1997: 

error message from tblgen
=============
Included from /home/wei/project/tx3/llvm-project/llvm/lib/Target/AArch64/AArch64.td:439:
/home/wei/project/tx3/llvm-project/llvm/lib/Target/AArch64/AArch64InstrInfo.td:961:5: error: 'CycloneModel' lacks information for 'AUTDZA'
    def DZA  : SignAuthZero<prefix_z, 0b10, !strconcat(asm, "dza")>;
    ^
In the end:
Incomplete schedule models found.
- Consider setting 'CompleteModel = 0' while developing new models.
- Pseudo instructions can be marked with 'hasNoSchedulingInfo = 1'.
- Instructions should usually have Sched<[...]> as a superclass, you may temporarily use an empty list.
- Instructions related to unsupported features can be excluded with list<Predicate> UnsupportedFeatures = [HasA,..,HasY]; in the processor model.

error: Incomplete schedule model
=================

Anyone has clue why we have this problem? How should I model these instructions in the .md file.

Thanks,


Repository:
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  https://reviews.llvm.org/D78129/new/

https://reviews.llvm.org/D78129