[PATCH] D79288: [AMDGPU][MC] Enabled 21-bit signed offsets for SMEM instructions

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp:369
+  const MCOperand &MO = MI.getOperand(OpNo);
+  assert(MO.isImm());
+
----------------
This assert is redundant, the getImm below will assert anyway


================
Comment at: llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp:372-373
+  auto Offset = MO.getImm();
+  if (AMDGPU::isVI(STI)) {
+    Offset &= 0xFFFFF;       // VI only supports 20-bit unsigned offsets.
+  }
----------------
Do we really need to explicitly clamp this here?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79288/new/

https://reviews.llvm.org/D79288